Datasheet KSZ8842-PMQL, KSZ8842-PMBL (Microchip) - 6

Micrel, Inc. KSZ8842-PMQL/PMBL TOS Priority Control Register 4 (Offset 0x486): TOSR4 . 60
TOS Priority Control Register 5 (Offset 0x488): TOSR5 . 61
TOS Priority Control Register 6 (Offset 0x48A): TOSR6. 62
TOS Priority Control Register 7 (Offset 0x490): TOSR7 . 62
TOS Priority Control Register 8 (Offset 0x492): TOSR8 . 63
Reserved (Offset 0x0494 -0x049A) . 63
Indirect Access Control Register (Offset 0x04A0): IACR . 64
Indirect Access Data Register 1 (Offset 0x04A2): IADR1 . 64
Indirect Access Data Register 2 (Offset 0x04A4): IADR2 . 64
Indirect Access Data Register 3 (Offset 0x04A6): IADR3 . 64
Indirect Access Data Register 4 (Offset 0x04A8): IADR4 . 64
Indirect Access Data Register 5 (Offset 0x04AA): IADR5 . 65
Reserved (Offset 0x04B0 -0x04BA) . 65
Reserved (Offset 0x04C0 –0x04CF) . 65
PHY 1 MII Basic Control Register (Offset 0x04D0): P1MBCR . 65
PHY 1 MII Basic Status Register (Offset 0x04D2): P1MBSR. 66
PHY 1 PHYID Low Register (Offset 0x04D4): PHY1ILR. 67
PHY 1 PHYID High Register (Offset 0x04D6): PHY1IHR . 67
PHY 1 Auto-Negotiation Advertisement Register (Offset 0x04D8): P1ANAR . 67
PHY 1 Auto-Negotiation Link Partner Ability Register (Offset 0x04DA): P1ANLPR. 68
PHY 2 MII Basic Control Register (Offset 0x04E0): P2MBCR . 68
PHY 2 MII Basic Status Register (Offset 0x04E2): P2MBSR. 69
PHY 2 PHYID Low Register (Offset 0x04E4): PHY2ILR . 70
PHY 2 PHYID High Register (Offset 0x04E6): PHY2IHR. 70
PHY 2 Auto-Negotiation Advertisement Register (Offset 0x04E8): P2ANAR . 70
PHY 2 Auto-Negotiation Link Partner Ability Register (Offset 0x04EA): P2ANLPR. 71
PHY1 LinkMD Control/Status (Offset 0x04F0): P1VCT. 72
PHY1 Special Control/Status Register (Offset 0x04F2): P1PHYCTRL. 72
PHY2 LinkMD Control/Status (Offset 0x04F4): P2VCT. 73
PHY2 Special Control/Status Register (Offset 0x04F6): P2PHYCTRL. 73
Reserved (Offset 0x04F8 -0x04FA). 73
Port 1 Control Register 1 (Offset 0x0500): P1CR1. 74
Port 1 Control Register 2 (Offset 0x0502): P1CR2. 75
Port 1 VID Control Register (Offset 0x0504): P1VIDCR. 76
Port 1 Control Register 3 (Offset 0x0506): P1CR3. 76
Port 1 Ingress Rate Control Register (Offset 0x0508): P1IRCR. 77
Port 1 Egress Rate Control Register (Offset 0x050A): P1ERCR . 79
Port 1 PHY Special Control/Status, LinkMD (Offset 0x0510): P1SCSLMD . 81
Port 1 Control Register 4 (Offset 0x0512): P1CR4. 82
Port 1 Status Register (Offset 0x0514): P1SR . 83
Port 1 Reserved (Offset 0x0516 – 0x051A). 84
Port 2 Control Register 1 (Offset 0x0520): P2CR1. 84
Port 2 Control Register 2 (Offset 0x0522): P2CR2. 85
Port 2 VID Control Register (Offset 0x0524): P2VIDCR. 86
Port 2 Control Register 3 (Offset 0x0526): P2CR3. 87
Port 2 Ingress Rate Control Register (Offset 0x0528): P2IRCR. 87
Port 2 Egress Rate Control Register (Offset 0x052A): P2ERCR . 89
Port 2 PHY Special Control/Status, LinkMD (Offset 0x0530): P2SCSLMD . 92
Port 2 Control Register 4 (Offset 0x0532): P2CR4. 92
Port 2 Status Register (Offset 0x0534): P2SR . 94
Port 2 Reserved (Offset 0x0536 – 0x053A). 95
Host Control Register 1 (Offset 0x0540): P3CR1 . 95
Host Control Register 2 (Offset 0x0542): P3CR2 . 96
Host VID Control Register (Offset 0x0544): P3VIDCR. 97
Host Control Register 3 (Offset 0x0546): P3CR3 . 97
Host Ingress Rate Control Register (Offset 0x0548): P3IRCR. 98
October 2007 6 M9999-100207-1.5