Datasheet KS8995MA, KS8995FQ (Microchip) - 2
| Manufacturer | Microchip |
| Description | Integrated 5-Port 10/100 Managed Switch |
| Pages / Page | 89 / 2 — Features. Applications |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
Features. Applications
Model Line for this Datasheet
Text Version of Document
Micrel, Inc. KS8995MA/FQ
Features
• Integrated switch with five MACs and five fast • MDC and MDI/O interface support to access the MII Ethernet transceivers fully-compliant to IEEE 802.3u PHY control registers (not all control registers) standard • MII local loopback support • Shared memory based switch fabric with fully non- blocking configuration • On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) • 1.4Gbps high-performance memory bandwidth • Wire-speed reception and transmission • 10BASE-T, 100BASE-TX, and 100BASE-FX modes • Integrated look-up engine with dedicated 1K MAC • Dual MII configuration: MII-Switch (MAC or PHY addresses mode MII) and MII-P5 (PHY mode MII). • Full duplex IEEE 802.3x and half-duplex back • IEEE 802.1q tag-based VLAN (16 VLANs, full-range pressure flow control VID) for DMZ port, WAN/LAN separation or inter- VLAN switch links • Comprehensive LED support • VLAN ID tag/untag options, per-port basis • 7-wire SNI support for legacy MAC interface • Programmable rate limiting 0Mbps to 100Mbps, • Automatic MDI/MDI-X crossover for plug-and-play ingress and egress port, rate options for high and • Disable automatic MDI/MDI-X option low priority, per-port basis in 32Kbps increments • Low power: • Flow control or drop packet rate limiting − Core: 1.8V (ingress port) − Digital I/O: 3.3V • Integrated MIB counters for fully-compliant statistics − gathering, 34 MIB counters per port Analog I/O: 3.3V • • Enable/Disable option for huge frame size up to 0.18µm CMOS technology 1916 bytes per frame • Temperature ranges: • IGMP v1/v2 snooping for multicast packet filtering − Commercial: 0°C to +70°C • Special tagging mode to send CPU info on ingress − Industrial: –40°C to +85°C packet’s port value • Available in 128-pin PQFP package • SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register configuration
Applications
• MAC-id based security lock option • Broadband gateway/firewall/VPN • Control registers configurable on-the-fly (port- • Integrated DSL or cable modem multi-port router priority, 802.1p/d/q, AN...) • Wireless LAN access point plus gateway • CPU read access to MAC forwarding table entries • Home networking expansion • 802.1d spanning tree protocol • Standalone 10/100 switch • • Port mirroring/monitoring/sniffing: ingress and/or Hotel/campus/MxU gateway egress traffic to any port or MII • Enterprise VoIP gateway/phone • Broadcast storm protection with % control – global • FTTx customer premise equipment and per-port basis • Managed media converter • Optimization for fiber-to-copper media conversion • Full-chip hardware power-down support (register configuration not saved) • Per-port based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: − Per port, 802.1p and DiffServ based • 802.1p/q tag insertion or removal on a per-port basis (egress) December 2012 2 M9999-121212-3.0
Features
• Integrated switch with five MACs and five fast • MDC and MDI/O interface support to access the MII Ethernet transceivers fully-compliant to IEEE 802.3u PHY control registers (not all control registers) standard • MII local loopback support • Shared memory based switch fabric with fully non- blocking configuration • On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) • 1.4Gbps high-performance memory bandwidth • Wire-speed reception and transmission • 10BASE-T, 100BASE-TX, and 100BASE-FX modes • Integrated look-up engine with dedicated 1K MAC • Dual MII configuration: MII-Switch (MAC or PHY addresses mode MII) and MII-P5 (PHY mode MII). • Full duplex IEEE 802.3x and half-duplex back • IEEE 802.1q tag-based VLAN (16 VLANs, full-range pressure flow control VID) for DMZ port, WAN/LAN separation or inter- VLAN switch links • Comprehensive LED support • VLAN ID tag/untag options, per-port basis • 7-wire SNI support for legacy MAC interface • Programmable rate limiting 0Mbps to 100Mbps, • Automatic MDI/MDI-X crossover for plug-and-play ingress and egress port, rate options for high and • Disable automatic MDI/MDI-X option low priority, per-port basis in 32Kbps increments • Low power: • Flow control or drop packet rate limiting − Core: 1.8V (ingress port) − Digital I/O: 3.3V • Integrated MIB counters for fully-compliant statistics − gathering, 34 MIB counters per port Analog I/O: 3.3V • • Enable/Disable option for huge frame size up to 0.18µm CMOS technology 1916 bytes per frame • Temperature ranges: • IGMP v1/v2 snooping for multicast packet filtering − Commercial: 0°C to +70°C • Special tagging mode to send CPU info on ingress − Industrial: –40°C to +85°C packet’s port value • Available in 128-pin PQFP package • SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register configuration
Applications
• MAC-id based security lock option • Broadband gateway/firewall/VPN • Control registers configurable on-the-fly (port- • Integrated DSL or cable modem multi-port router priority, 802.1p/d/q, AN...) • Wireless LAN access point plus gateway • CPU read access to MAC forwarding table entries • Home networking expansion • 802.1d spanning tree protocol • Standalone 10/100 switch • • Port mirroring/monitoring/sniffing: ingress and/or Hotel/campus/MxU gateway egress traffic to any port or MII • Enterprise VoIP gateway/phone • Broadcast storm protection with % control – global • FTTx customer premise equipment and per-port basis • Managed media converter • Optimization for fiber-to-copper media conversion • Full-chip hardware power-down support (register configuration not saved) • Per-port based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: − Per port, 802.1p and DiffServ based • 802.1p/q tag insertion or removal on a per-port basis (egress) December 2012 2 M9999-121212-3.0
