Datasheet KS8995X (Microchip) - 4

KS8995X Micrel Table of Contents
System Level Applications . 6
Pin Description (by Number) . 8
Pin Description (by Name) . 13
Pin Configuration . 18
Introduction . 19 Functional Overview: Physical Layer Transceiver . 19
100BaseTX Transmit . 19
100BaseTX Receive . 19
PLL Clock Synthesizer . 19
Scrambler/De-scrambler (100BaseTX only) . 19
100BaseFX Operation . 19
100BaseFX Signal Detection . 20
100BaseFX Far End Fault . 20
10BaseT Transmit . 20
10BaseT Receive . 20
Power Management . 20
MDI/MDI-X Auto Crossover . 20
Auto-Negotiation . 20
Functional Overview: Switch Core . 21
Address Look Up . 21
Learning . 21 Migration . 21 Aging . 21 Switching Engine . 21
MAC (Media Access Controller) Operation . 22
Inter-Packet Gap . 22
Backoff Algorithm . 22
Late Collision . 22
Illegal Frame . 22
Flow Control . 22
Half-Duplex Back Pressure . 22
Broadcast Storm Protection . 23
MII Interface Operation . 23
SNI Interface Operation . 25
Advanced Functionality . 25
QoS Support . 25
Rate Limit Support . 27
Configuration Interface . 28
I2C Master Serial Bus Configuration . 28
MII Management Interface (MIIM) . 28
Register Map . 29 Global Registers . 29
Register 0 (0x00): Chip ID0 . 29
Register 1 (0x01): Chip ID1/Start Switch . 29
Register 2 (0x02): Global Control 0 . 29
Register 3 (0x03): Global Control 1 . 30
Register 4 (0x04): Global Control 2 . 31
Register 5 (0x05): Global Control 3 . 31
Register 6 (0x06): Global Control 4 . 32
Register 7 (0x07): Global Control 5 . 32
M9999-120403 4 December 2003