Datasheet LAN9313, LAN9313i (Microchip) - 10

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LAN9313/LAN9313i
2.2.3 SWITCH FABRIC The Switch Fabric consists of the following major function blocks: •
10/100 MACs
There is one 10/100 Ethernet MAC per switch fabric port, which provides basic 10/100 Ethernet functionality, including transmission deferral, collision back-off/retry, TX/RX FCS checking/generation, TX/RX pause flow con- trol, and transmit back pressure. The 10/100 MACs act as an interface between the switch engine and the 10/100 PHYs (for ports 1 and 2). The port 0 10/100 MAC interfaces the switch engine to the external MAC/PHY (see Sec- tion 2.3, "Modes of Operation"). Each 10/100 MAC includes RX and TX FIFOs and per port statistic counters. •
Switch Engine
This block, consisting of a 3 port VLAN layer 2 switching engine, provides the control for all forwarding/filtering rules and supports untagged, VLAN tagged, and priority tagged frames. The switch engine provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, and port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. A 1K entry forwarding table provides ample room for MAC address for- warding tables. •
Buffer Manager
This block controls the free buffer space, multi-level transmit queues, transmission scheduling, and packet drop- ping of the switch fabric. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed. Each port is allocated 1a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the Buf- fer Manager block. •
Switch CSRs
This block contains all switch related control and status registers, and allows all aspects of the switch fabric to be managed. These registers are indirectly accessible via the system control and status registers 2.2.4 ETHERNET PHYS The LAN9313/LAN9313i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of an external MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set. 2.2.5 PHY MANAGEMENT INTERFACE (PMI) The PHY Management Interface (PMI) is used to serially access the internal PHYs as well as the external PHY on the MII pins (in MAC mode only, see Section 2.3, "Modes of Operation"). The PMI implements the IEEE 802.3 management protocol, providing read/write commands for PHY configuration. 2.2.6 SPI/I2C SLAVE CONTROLLER This module provides an SPI/I2C slave interface which can be used for CPU serial management of the LAN9313/LAN9313i. The SPI slave controller allows CPU access to all system CSRs for configuration and management. The SPI slave con- troller supports single register and multiple register read and write commands. Multiple read and multiple write com- mands support incrementing, decrementing, and static addressing. The I2C slave controller implements the low level I2C slave serial interface (start and stop condition detection, data bit transmission/reception, and acknowledge generation/reception), handles the slave command protocol, and performs system register reads and writes. The I2C slave controller conforms to the Philips I2C-Bus Specification. A list of management modes and configurations settings for these modes is discussed in Section 2.3, "Modes of Oper- ation" DS00002288A-page 10  2008-2016 Microchip Technology Inc. Document Outline 1.0 Preface 1.1 General Terms 1.2 Buffer Types TABLE 1-1: Buffer Types 1.3 Register Nomenclature TABLE 1-2: Register Bit Types 2.0 Introduction 2.1 General Description 2.2 Block Diagram FIGURE 2-1: Internal LAN9313/LAN9313i Block Diagram 2.2.1 System Clocks/Reset/PME Controller 2.2.2 System Interrupt Controller 2.2.3 Switch Fabric 2.2.4 Ethernet PHYs 2.2.5 PHY Management Interface (PMI) 2.2.6 SPI/I2C Slave Controller 2.2.7 SMI Slave Controller 2.2.8 EEPROM Controller/Loader 2.2.9 1588 Time Stamp 2.2.10 GPIO/LED Controller 2.3 Modes of Operation 2.3.1 MAC Mode 2.3.2 PHY Mode 2.3.3 Management Modes TABLE 2-1: LAN9313/LAN9313i Modes FIGURE 2-2: System Block Diagrams - MAC/PHY Modes of Operation 3.0 Pin Description and Configuration 3.1 Pin Diagrams 3.1.1 128-VTQFP Pin Diagram FIGURE 3-1: LAN9313 128-VTQFP Pin Assignments (TOP VIEW) 3.1.2 128-XVTQFP Pin Diagram FIGURE 3-2: LAN9313/LAN9313i 128-XVTQFP Pin Assignments (TOP VIEW) 3.2 Pin Descriptions TABLE 3-1: LAN Port 1 Pins TABLE 3-2: LAN Port 2 Pins TABLE 3-3: LAN Port 1 & 2 Power and Common Pins TABLE 3-4: LAN Port 0(External MII) Pins TABLE 3-5: Dedicated Configuration Strap Pins TABLE 3-6: EEPROM Pins TABLE 3-7: Serial Management Pins TABLE 3-8: Miscellaneous Pins TABLE 3-9: PLL Pins TABLE 3-10: Core and I/O Power and Ground Pins TABLE 3-11: No-Connect Pins 4.0 Clocking, Resets, and Power Management 4.1 Clocks 4.2 Resets TABLE 4-1: Reset Sources and Affected LAN9313/LAN9313i Circuitry 4.2.1 Chip-Level Resets 4.2.2 Multi-Module Resets 4.2.3 Single-Module Resets 4.2.4 Configuration Straps TABLE 4-2: Soft-Strap Configuration Strap Definitions TABLE 4-3: Hard-Strap Configuration Strap Definitions 4.3 Power Management 4.3.1 Port 1 & 2 PHY Power Management 5.0 System Interrupts 5.1 Functional Overview 5.2 Interrupt Sources FIGURE 5-1: Functional Interrupt Register Hierarchy 5.2.1 1588 Time Stamp Interrupts 5.2.2 Switch Fabric Interrupts 5.2.3 Ethernet PHY Interrupts 5.2.4 GPIO Interrupts 5.2.5 General Purpose Timer Interrupt 5.2.6 Software Interrupt 5.2.7 Device Ready Interrupt 6.0 Switch Fabric 6.1 Functional Overview 6.2 Switch Fabric CSRs 6.2.1 Switch Fabric CSR Writes FIGURE 6-1: Switch Fabric CSR Write Access Flow Diagram 6.2.2 Switch Fabric CSR Reads FIGURE 6-2: Switch Fabric CSR Read Access Flow Diagram 6.2.3 Flow Control Enable Logic TABLE 6-1: Switch Fabric Flow Control Enable Logic 6.3 10/100 Ethernet MACs 6.3.1 Receive MAC 6.3.2 Transmit MAC 6.4 Switch Engine (SWE) 6.4.1 MAC Address Lookup Table FIGURE 6-3: ALR Table Entry Structure 6.4.2 Forwarding Rules 6.4.3 Transmit Priority Queue Selection FIGURE 6-4: Switch Engine Transmit Queue Selection FIGURE 6-5: Switch Engine Transmit Queue Calculation 6.4.4 VLAN Support TABLE 6-2: VLAN Table Entry Structure 6.4.5 Spanning Tree Support TABLE 6-3: Spanning Tree States 6.4.6 Ingress Flow Metering and Coloring TABLE 6-4: Typical Ingress Rate Settings FIGURE 6-6: Switch Engine Ingress Flow Priority Selection FIGURE 6-7: Switch Engine Ingress Flow Priority Calculation 6.4.7 Broadcast Storm Control TABLE 6-5: Typical Broadcast Rate Settings 6.4.8 IPv4 IGMP Support 6.4.9 Port Mirroring 6.4.10 Host CPU Port Special Tagging 6.4.11 Counters 6.5 Buffer Manager (BM) 6.5.1 Packet Buffer Allocation 6.5.2 Random Early Discard (RED) 6.5.3 Transmit Queues 6.5.4 Transmit Priority Queue Servicing 6.5.5 Egress Rate Limiting (Leaky Bucket) TABLE 6-6: Typical Egress Rate Settings 6.5.6 Adding, Removing, and Changing VLAN Tags FIGURE 6-8: Hybrid Port Tagging and Un-tagging 6.5.7 Counters 6.6 Switch Fabric Interrupts 7.0 Ethernet PHYs 7.1 Functional Overview 7.1.1 PHY Addressing TABLE 7-1: Default PHY Serial MII Addressing 7.2 Port 1 & 2 PHYs FIGURE 7-1: Port x PHY Block Diagram 7.2.1 100BASE-TX Transmit FIGURE 7-2: 100BASE-TX Transmit Data Path TABLE 7-2: 4B/5B Code Table 7.2.2 100BASE-TX Receive FIGURE 7-3: 100BASE-TX Receive Data Path 7.2.3 10BASE-T Transmit 7.2.4 10BASE-T Receive 7.2.5 PHY Auto-negotiation 7.2.6 HP Auto-MDIX FIGURE 7-4: Direct Cable Connection vs. Cross-Over Cable Connection 7.2.7 MII MAC Interface 7.2.8 PHY Management Control TABLE 7-3: PHY Interrupt Sources 7.2.9 PHY Power-Down Modes 7.2.10 PHY Resets 7.2.11 LEDs 7.2.12 Required Ethernet Magnetics 7.3 Virtual PHY 7.3.1 Virtual PHY Auto-Negotiation 7.3.2 Virtual PHY in MAC Modes 7.3.3 Virtual PHY Resets 8.0 Serial Management 8.1 Functional Overview 8.2 I2C/Microwire Master EEPROM Controller TABLE 8-1: I2C/Microwire Master Serial Management Pins Characteristics 8.2.1 EEPROM Controller Operation FIGURE 8-1: EEPROM Access Flow Diagram 8.2.2 I2C EEPROM TABLE 8-2: I2C EEPROM Size Ranges FIGURE 8-2: I2C Cycle FIGURE 8-3: I2C EEPROM Addressing FIGURE 8-4: I2C EEPROM Byte Read FIGURE 8-5: I2C EEPROM Sequential Byte Reads FIGURE 8-6: I2C EEPROM Byte Write 8.2.3 Microwire EEPROM TABLE 8-3: Microwire EEPROM Size Ranges TABLE 8-4: Microwire Command Set for 7 Address Bits TABLE 8-5: Microwire Command Set for 9 Address Bits TABLE 8-6: Microwire Command Set for 11 Address Bits FIGURE 8-7: EEPROM ERASE Cycle FIGURE 8-8: EEPROM ERAL Cycle FIGURE 8-9: EEPROM EWDS Cycle FIGURE 8-10: EEPROM EWEN Cycle FIGURE 8-11: EEPROM READ Cycle FIGURE 8-12: EEPROM WRITE Cycle FIGURE 8-13: EEPROM WRAL Cycle 8.2.4 EEPROM Loader TABLE 8-7: EEPROM Contents Format Overview FIGURE 8-14: EEPROM Loader Flow Diagram TABLE 8-8: EEPROM Configuration Bits 8.3 SPI/I2C Slave Controller TABLE 8-9: SPI / I2C Slave Serial Management Pins Characteristics 8.4 SPI Slave Operation TABLE 8-10: Supported SPI Instructions 8.4.1 SPI Read Sequence FIGURE 8-15: SPI Reads 8.4.2 SPI Write Sequence FIGURE 8-16: SPI Writes 8.5 I2C Slave Operation 8.5.1 I2C Slave Command Format FIGURE 8-17: I2C Slave Addressing 8.5.2 I2C Slave Read Sequence FIGURE 8-18: I2C Slave Reads 8.5.3 I2C Slave Write Sequence FIGURE 8-19: I2C Slave Writes 9.0 MII Management 9.1 Functional Overview 9.2 SMI Slave Controller TABLE 9-1: SMI Frame Format 9.2.1 Read Sequence 9.2.2 Write Sequence 9.3 PHY Management Interface (PMI) TABLE 9-2: MII Management Frame Format 9.3.1 EEPROM Loader PHY Register Access 9.4 MII Mode Multiplexer 9.4.1 MAC Mode Unmanaged FIGURE 9-1: MII Mux Management Path Connections - MAC Mode Unmanaged 9.4.2 MAC Mode SMI Managed FIGURE 9-2: MII Mux Management Path Connections - MAC Mode SMI Managed 9.4.3 MAC Mode I2C/SPI Managed FIGURE 9-3: MII Mux Management Path Connections - MAC Mode I2C/SPI Managed 9.4.4 PHY Mode Unmanaged FIGURE 9-4: MII Mux Management Path Connections - PHY Mode Unmanaged 9.4.5 PHY Mode SMI Managed FIGURE 9-5: MII Mux Management Path Connections - PHY Mode SMI Managed 9.4.6 PHY Mode I2C/SPI Managed FIGURE 9-6: MII Mux Management Path Connections - PHY Mode I2C/SPI Managed 10.0 IEEE 1588 Hardware Time Stamp Unit 10.1 Functional Overview 10.1.1 IEEE 1588 10.1.2 Block Diagram FIGURE 10-1: IEEE 1588 Block Diagram 10.2 IEEE 1588 Time Stamp TABLE 10-1: IEEE 1588 Message Type Detection FIGURE 10-2: IEEE 1588 Message Time Stamp Point TABLE 10-2: Time Stamp Capture Delay 10.2.1 Capture Locking 10.2.2 PTP Message Detection TABLE 10-3: PTP Multicast Addresses 10.3 IEEE 1588 Clock TABLE 10-4: Typical IEEE 1588 Clock Addend Values 10.4 IEEE 1588 Clock/Events 10.5 IEEE 1588 GPIOs 10.6 IEEE 1588 Interrupts 11.0 General Purpose Timer & Free-Running Clock 11.1 General Purpose Timer 11.2 Free-Running Clock 12.0 GPIO/LED Controller 12.1 Functional Overview 12.2 GPIO Operation 12.2.1 GPIO IEEE 1588 Timestamping 12.2.2 GPIO Interrupts 12.3 LED Operation TABLE 12-1: LED Operation as a Function of LED_CFG[9:8] 13.0 Register Descriptions FIGURE 13-1: LAN9313/LAN9313i Base Register Memory Map 13.1 System Control and Status Registers TABLE 13-1: System Control and Status Registers 13.1.1 Interrupts 13.1.2 GPIO/LED 13.1.3 EEPROM 13.1.4 IEEE 1588 13.1.5 Switch Fabric TABLE 13-2: SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Byte Ordering FIGURE 13-2: Example SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Setup TABLE 13-3: Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map 13.1.6 PHY Management Interface (PMI) 13.1.7 Virtual PHY TABLE 13-4: Virtual PHY MII Serially Adressable Register Index TABLE 13-5: Emulated Link Partner Pause Flow Control Ability Default Values TABLE 13-6: Emulated Link Partner Default Advertised Ability 13.1.8 Miscellaneous 13.2 Ethernet PHY Control and Status Registers 13.2.1 Virtual PHY Registers 13.2.2 Port 1 & 2 PHY Registers TABLE 13-7: Port 1 & 2 PHY MII Serially Adressable Registers TABLE 13-8: 10BASE-T Full Duplex Advertisement Default Value TABLE 13-9: 10BASE-T Half Duplex Advertisement Bit Default Value TABLE 13-10: MODE[2:0] Definitions TABLE 13-11: Auto-MDIX Enable and Auto-MDIX State Bit Functionality 13.3 Switch Fabric Control and Status Registers TABLE 13-12: Indirectly Accessible Switch Control and Status Registers 13.3.1 General Switch CSRs 13.3.2 Switch Port 0, Port 1, and Port 2 CSRs 13.3.3 Switch Engine CSRs TABLE 13-13: Metering/Color Table Register Descriptions 13.3.4 Buffer Manager CSRs 14.0 Operational Characteristics 14.1 Absolute Maximum Ratings* 14.2 Operating Conditions** 14.3 Power Consumption TABLE 14-1: Supply and Current (10BASE-T Full-Duplex) TABLE 14-2: Supply and Current (100BASE-TX Full-Duplex) 14.4 DC Specifications TABLE 14-3: I/O Buffer Characteristics TABLE 14-4: 100BASE-TX Transceiver Characteristics TABLE 14-5: 10BASE-T Transceiver Characteristics 14.5 AC Specifications 14.5.1 Equivalent Test Load FIGURE 14-1: Output Equivalent Test Load 14.5.2 Reset and Configuration Strap Timing FIGURE 14-2: nRST Reset Pin Timing TABLE 14-6: nRST Reset Pin Timing Values 14.5.3 Power-On Configuration Strap Valid Timing FIGURE 14-3: Power-On Configuration Strap Latching Timing TABLE 14-7: Power-On Configuration Strap Latching Timing Values 14.5.4 Microwire Timing FIGURE 14-4: Microwire Timing TABLE 14-8: Microwire Timing Values 14.5.5 SPI Slave Timing FIGURE 14-5: SPI Slave Timing TABLE 14-9: SPI Slave Timing Values 14.6 Clock Circuit TABLE 14-10: LAN9313/LAN9313i Crystal Specifications 15.0 Package Outlines 15.1 128-VTQFP Package Outline FIGURE 15-1: 128-vTQFP, 14x14x1.0mm body, 0.4mm Pitch FIGURE 15-2: 128-VTQFP Recommended PCB Land Pattern 15.2 128-XVTQFP Package Outline FIGURE 15-3: 128-XVTQFP 14x14x1.0mm Body, 0.4mm Pitch Appendix A: Data sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service