Datasheet LTC1863L, LTC1867L (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Micropower, 3V, 16-Bit, 8-Channel 175ksps ADCs |
| Pages / Page | 16 / 8 — TYPICAL CONNECTION DIAGRAM. TEST CIRCUITS. Load Circuits for Access … |
| File Format / Size | PDF / 256 Kb |
| Document Language | English |
TYPICAL CONNECTION DIAGRAM. TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay
Model Line for this Datasheet
Text Version of Document
LTC1863L/LTC1867L
TYPICAL CONNECTION DIAGRAM
±1.25V + CH0 VDD 2.7V TO 3.6V DIFFERENTIAL 10µF INPUTS – CH1 GND CH2 SDI CH3 LTC1863L/ SDO LTC1867L DIGITAL 2.5V SINGLE-ENDED + I/O CH4 SCK INPUT CH5 CS/CONV CH6 VREF 1.25V 2.2µF CH7/COM REFCOMP 2.5V 10µF 1863L7L TCD
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
2.7V 2.7V 3k 3k SDO SDO SDO SDO 3k CL CL 3k CL CL (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1863L7L TC01 1863L7L TC02
TIMING DIAGRAMS t2 (SDO Valid After SCK
↓
) t1 (For Short Pulse Mode) t3 (SDO Valid Hold Time After SCK
↓
)
t1 t2 CS/CONV 50% 50% SCK 0.45V 1863L7L TD01a t3 1.9V SDO 0.45V 1863L7L TD01b
t5 (SDI Setup Time Before SCK
↑
) t4 (SDO Valid After CS/CONV
↓
) t6 (SDI Hold Time After SCK
↑
)
t4 t t 5 6 CS/CONV 1.9V 0.45V SCK Hi-Z 1.9V SDO 1.9V 1.9V 0.45V SDI 0.45V 0.45V 1863L7L TD01c 1863L7L TD01d
t7 (SLEEP Mode Wake-Up Time) t8 (BUS Relinquish Time)
t7 t8 SCK 50% 1.9V CS/CONV SLEEP BIT (SLP = 0) READ-IN 90% Hi-Z CS/CONV 50% SDO 10% 1863L7L TD01f 1863L7L TD01e 1863l7lfe 8 For more information www.linear.com/LTC1863L Document Outline Description Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Package Description Related Parts
TYPICAL CONNECTION DIAGRAM
±1.25V + CH0 VDD 2.7V TO 3.6V DIFFERENTIAL 10µF INPUTS – CH1 GND CH2 SDI CH3 LTC1863L/ SDO LTC1867L DIGITAL 2.5V SINGLE-ENDED + I/O CH4 SCK INPUT CH5 CS/CONV CH6 VREF 1.25V 2.2µF CH7/COM REFCOMP 2.5V 10µF 1863L7L TCD
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
2.7V 2.7V 3k 3k SDO SDO SDO SDO 3k CL CL 3k CL CL (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1863L7L TC01 1863L7L TC02
TIMING DIAGRAMS t2 (SDO Valid After SCK
↓
) t1 (For Short Pulse Mode) t3 (SDO Valid Hold Time After SCK
↓
)
t1 t2 CS/CONV 50% 50% SCK 0.45V 1863L7L TD01a t3 1.9V SDO 0.45V 1863L7L TD01b
t5 (SDI Setup Time Before SCK
↑
) t4 (SDO Valid After CS/CONV
↓
) t6 (SDI Hold Time After SCK
↑
)
t4 t t 5 6 CS/CONV 1.9V 0.45V SCK Hi-Z 1.9V SDO 1.9V 1.9V 0.45V SDI 0.45V 0.45V 1863L7L TD01c 1863L7L TD01d
t7 (SLEEP Mode Wake-Up Time) t8 (BUS Relinquish Time)
t7 t8 SCK 50% 1.9V CS/CONV SLEEP BIT (SLP = 0) READ-IN 90% Hi-Z CS/CONV 50% SDO 10% 1863L7L TD01f 1863L7L TD01e 1863l7lfe 8 For more information www.linear.com/LTC1863L Document Outline Description Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Package Description Related Parts
