Datasheet AD5749 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Industrial Current Out Driver, Single-Supply, 55 V Maximum Supply, Programmable Ranges |
| Pages / Page | 28 / 8 — AD5749. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. LT/. … |
| Revision | D |
| File Format / Size | PDF / 553 Kb |
| Document Language | English |
AD5749. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. LT/. /IF. SET. SEL. SDO 1. 24 DNC. CLRSEL 2. 23 DNC. CLEAR 3. 22 GND. DVCC 4
Text Version of Document
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AD5749 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P T T M L EC U TE A LT/ /IF U SET SEL C E W N FA R H NC NC NC NC 32 31 30 29 28 27 26 25 SDO 1 24 DNC CLRSEL 2 23 DNC CLEAR 3 22 GND AD5749 DVCC 4 21 GND TOP VIEW GND 5 20 DNC (Not to Scale) SYNC/RSET 6 19 DNC SCLK/OUTEN 7 18 IOUT SDIN/R0 8 17 AVDD 9 10 11 12 13 14 15 16 1 2 3 2 1 N D R R R T T EF X X VI VR GN AD2/ AD1/ AD0/ RE RE NOTES 1. NC = NO CONNECT. CAN BE TIED TO GND.
004
2. DNC = DO NOT CONNECT.
23-
3. THE EXPOSED PADDLE IS TIED TO GND.
089 Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 SDO Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin is a CMOS output. 2 CLRSEL In hardware or software mode, this pin selects the clear value, either zero scale or midscale. In software mode, this pin is implemented as a logic OR with the internal CLRSEL bit. 3 CLEAR Active High Input. Asserting this pin sets the output current to zero-scale code or midscale of range selected (user selectable). CLEAR is a logic OR with the internal CLEAR bit. See the Asynchronous Clear (CLEAR) section for more details. 4 DVCC Digital Power Supply. 5 GND Ground Connection. 6 SYNC/RSET Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data into the AD5749 and also updates the output. Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense resistor is used. If RSET = 0, the external sense resistor is chosen. If RSET = 1, the internal sense resistor is chosen. 7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin. 8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK. Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output current range setting on the part. 9 AD2/R1 Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD0 and AD1, allows up to eight devices to be addressed on one bus. Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output current range setting on the part. Rev. D | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY TIMING CHARACTERISTICS Timing Diagrams ESD CAUTION SOFTWARE MODE CURRENT OUTPUT ARCHITECTURE DRIVING INDUCTIVE LOADS POWER-ON STATE OF THE AD5749 DEFAULT REGISTERS AT POWER-ON RESET FUNCTION OUTEN SOFTWARE CONTROL Input Shift Register Status Bit Read Operation HARDWARE CONTROL TRANSFER FUNCTION OUTPUT FAULT ALERT—SOFTWARE MODE OUTPUT FAULT ALERT—HARDWARE MODE ASYNCHRONOUS CLEAR (CLEAR) EXTERNAL CURRENT SETTING RESISTOR PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING ORDERING GUIDE
AD5749 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P T T M L EC U TE A LT/ /IF U SET SEL C E W N FA R H NC NC NC NC 32 31 30 29 28 27 26 25 SDO 1 24 DNC CLRSEL 2 23 DNC CLEAR 3 22 GND AD5749 DVCC 4 21 GND TOP VIEW GND 5 20 DNC (Not to Scale) SYNC/RSET 6 19 DNC SCLK/OUTEN 7 18 IOUT SDIN/R0 8 17 AVDD 9 10 11 12 13 14 15 16 1 2 3 2 1 N D R R R T T EF X X VI VR GN AD2/ AD1/ AD0/ RE RE NOTES 1. NC = NO CONNECT. CAN BE TIED TO GND.
004
2. DNC = DO NOT CONNECT.
23-
3. THE EXPOSED PADDLE IS TIED TO GND.
089 Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 SDO Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin is a CMOS output. 2 CLRSEL In hardware or software mode, this pin selects the clear value, either zero scale or midscale. In software mode, this pin is implemented as a logic OR with the internal CLRSEL bit. 3 CLEAR Active High Input. Asserting this pin sets the output current to zero-scale code or midscale of range selected (user selectable). CLEAR is a logic OR with the internal CLEAR bit. See the Asynchronous Clear (CLEAR) section for more details. 4 DVCC Digital Power Supply. 5 GND Ground Connection. 6 SYNC/RSET Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data into the AD5749 and also updates the output. Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense resistor is used. If RSET = 0, the external sense resistor is chosen. If RSET = 1, the internal sense resistor is chosen. 7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin. 8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK. Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output current range setting on the part. 9 AD2/R1 Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD0 and AD1, allows up to eight devices to be addressed on one bus. Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output current range setting on the part. Rev. D | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY TIMING CHARACTERISTICS Timing Diagrams ESD CAUTION SOFTWARE MODE CURRENT OUTPUT ARCHITECTURE DRIVING INDUCTIVE LOADS POWER-ON STATE OF THE AD5749 DEFAULT REGISTERS AT POWER-ON RESET FUNCTION OUTEN SOFTWARE CONTROL Input Shift Register Status Bit Read Operation HARDWARE CONTROL TRANSFER FUNCTION OUTPUT FAULT ALERT—SOFTWARE MODE OUTPUT FAULT ALERT—HARDWARE MODE ASYNCHRONOUS CLEAR (CLEAR) EXTERNAL CURRENT SETTING RESISTOR PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING ORDERING GUIDE
