Datasheet AD420 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Serial Input 16-Bit 4 mA-20 mA, 0 mA-20 mA DAC |
| Pages / Page | 16 / 9 — Data Sheet. AD420. THEORY OF OPERATION. VCC. VLL 2. REFERENCE. 4kΩ. 40Ω. … |
| File Format / Size | PDF / 349 Kb |
| Document Language | English |
Data Sheet. AD420. THEORY OF OPERATION. VCC. VLL 2. REFERENCE. 4kΩ. 40Ω. REF OUT 14. 19 BOOST. REF IN 15. DATA OUT 10. CLOCK. 18 I. OUT. CLEAR 6
Model Line for this Datasheet
Text Version of Document
Data Sheet AD420 THEORY OF OPERATION
The AD420 uses a sigma-delta (Σ-Δ) architecture to carry out approximately one volt remaining of drive capability (when the digital-to-analog conversion. This architecture is particularly the gate of the output PMOS transistor nearly reaches ground). well suited for the relatively low bandwidth requirements of the Thus the FAULT DETECT output activates slightly before the industrial control environment because of its inherent compliance limit is reached. Since the comparison is made monotonicity at high resolution. within the feedback loop of the output amplifier, the output In the AD420 a second order modulator is used to keep com- accuracy is maintained by its open-loop gain, and no output plexity and die size to a minimum. The single bit stream from error occurs before the fault detect output becomes active. the modulator controls a switched current source that is then The 3-wire digital interface, comprising DATA IN, CLOCK, filtered by two, continuous time resistor-capacitor sections. and LATCH, interfaces to all commonly used serial micropro- The capacitors are the only external components that have to be cessors without the addition of any external glue logic. Data is added for standard current-out operation. The filtered current loaded into an input register under control of CLOCK and is is amplified and mirrored to the supply rail so that the application loaded to the DAC when LATCH is strobed. If a user wants to simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA minimize the number of galvanic isolators in an intrinsical y current source output with respect to ground. The AD420 safe application, the AD420 can be configured to run in is manufactured on a BiCMOS process that is well suited to asynchronous mode. This mode is selected by connecting the implementing low voltage digital logic with high performance LATCH pin to VCC through a current limiting resistor. The data and high voltage analog circuitry. must then be combined with a start and stop bit to frame the The AD420 can also provide a voltage output instead of a current information and trigger the internal LATCH signal. loop output if desired. The addition of a single external amplifier
VCC
al ows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or ±10 V.
23 VLL 2 REFERENCE
The AD420 has a loop fault detection circuit that warns if the
4kΩ 40Ω REF OUT 14
voltage at I
19 BOOST
OUT attempts to rise above the compliance range, due
AD420
to an open-loop circuit or insufficient power supply voltage. The
REF IN 15
FAULT DETECT is an active low open drain signal so that one
DATA OUT 10 CLOCK 18 I
can connect several AD420s together to one pul -up resistor for
OUT CLEAR 6 DATA I/P 17 VOUT
global error detection. The pul -up resistor can be tied to the
LATCH 7 REGISTER SWITCHED 16-BIT CURRENT 8 1.25kΩ
V
CLOCK DAC
LL pin, or an external +5 V logic supply.
SOURCES 9 FAULT DATA IN AND 3 DETECT
The I
FILTERING
OUT current is controlled by a PMOS transistor and an
RANGE SELECT 1 5
internal amplifier as shown in the functional block diagram.
RANGE 4
The internal circuitry that develops the fault output avoids
SELECT 2 16 20 21 11
using a comparator with window limits since this would require 005
OFFSET CAP 1 CAP 2 GND
an actual output error before the FAULT DETECT output
TRIM
00494- becomes active. Instead, the signal is generated when the Figure 5. Functional Block Diagram internal amplifier in the output stage of the AD420 has less than Rev. I | Page 9 of 16 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING REQUIREMENTS THREE-WIRE INTERFACE THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT ASYNCHRONOUS INTERFACE TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION CURRENT OUTPUT DRIVING INDUCTIVE LOADS VOLTAGE-MODE OUTPUT OPTIONAL SPAN AND ZERO TRIM THREE-WIRE INTERFACE USING MULTIPLE DACS WITH FAULT DETECT ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS MICROPROCESSOR INTERFACE AD420-TO-MC68HC11 (SPI BUS) INTERFACE AD420 TO MICROWIRE INTERFACE EXTERNAL BOOST FUNCTION AD420 PROTECTION TRANSIENT VOLTAGE PROTECTION BOARD LAYOUT AND GROUNDING POWER SUPPLIES AND DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE
The AD420 uses a sigma-delta (Σ-Δ) architecture to carry out approximately one volt remaining of drive capability (when the digital-to-analog conversion. This architecture is particularly the gate of the output PMOS transistor nearly reaches ground). well suited for the relatively low bandwidth requirements of the Thus the FAULT DETECT output activates slightly before the industrial control environment because of its inherent compliance limit is reached. Since the comparison is made monotonicity at high resolution. within the feedback loop of the output amplifier, the output In the AD420 a second order modulator is used to keep com- accuracy is maintained by its open-loop gain, and no output plexity and die size to a minimum. The single bit stream from error occurs before the fault detect output becomes active. the modulator controls a switched current source that is then The 3-wire digital interface, comprising DATA IN, CLOCK, filtered by two, continuous time resistor-capacitor sections. and LATCH, interfaces to all commonly used serial micropro- The capacitors are the only external components that have to be cessors without the addition of any external glue logic. Data is added for standard current-out operation. The filtered current loaded into an input register under control of CLOCK and is is amplified and mirrored to the supply rail so that the application loaded to the DAC when LATCH is strobed. If a user wants to simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA minimize the number of galvanic isolators in an intrinsical y current source output with respect to ground. The AD420 safe application, the AD420 can be configured to run in is manufactured on a BiCMOS process that is well suited to asynchronous mode. This mode is selected by connecting the implementing low voltage digital logic with high performance LATCH pin to VCC through a current limiting resistor. The data and high voltage analog circuitry. must then be combined with a start and stop bit to frame the The AD420 can also provide a voltage output instead of a current information and trigger the internal LATCH signal. loop output if desired. The addition of a single external amplifier
VCC
al ows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or ±10 V.
23 VLL 2 REFERENCE
The AD420 has a loop fault detection circuit that warns if the
4kΩ 40Ω REF OUT 14
voltage at I
19 BOOST
OUT attempts to rise above the compliance range, due
AD420
to an open-loop circuit or insufficient power supply voltage. The
REF IN 15
FAULT DETECT is an active low open drain signal so that one
DATA OUT 10 CLOCK 18 I
can connect several AD420s together to one pul -up resistor for
OUT CLEAR 6 DATA I/P 17 VOUT
global error detection. The pul -up resistor can be tied to the
LATCH 7 REGISTER SWITCHED 16-BIT CURRENT 8 1.25kΩ
V
CLOCK DAC
LL pin, or an external +5 V logic supply.
SOURCES 9 FAULT DATA IN AND 3 DETECT
The I
FILTERING
OUT current is controlled by a PMOS transistor and an
RANGE SELECT 1 5
internal amplifier as shown in the functional block diagram.
RANGE 4
The internal circuitry that develops the fault output avoids
SELECT 2 16 20 21 11
using a comparator with window limits since this would require 005
OFFSET CAP 1 CAP 2 GND
an actual output error before the FAULT DETECT output
TRIM
00494- becomes active. Instead, the signal is generated when the Figure 5. Functional Block Diagram internal amplifier in the output stage of the AD420 has less than Rev. I | Page 9 of 16 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING REQUIREMENTS THREE-WIRE INTERFACE THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT ASYNCHRONOUS INTERFACE TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION CURRENT OUTPUT DRIVING INDUCTIVE LOADS VOLTAGE-MODE OUTPUT OPTIONAL SPAN AND ZERO TRIM THREE-WIRE INTERFACE USING MULTIPLE DACS WITH FAULT DETECT ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS MICROPROCESSOR INTERFACE AD420-TO-MC68HC11 (SPI BUS) INTERFACE AD420 TO MICROWIRE INTERFACE EXTERNAL BOOST FUNCTION AD420 PROTECTION TRANSIENT VOLTAGE PROTECTION BOARD LAYOUT AND GROUNDING POWER SUPPLIES AND DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE
