Datasheet ADF5002 (Analog Devices) - 5

ADF5002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 D D D D N D D N G V V G 6 5 4 3 1 1 1 1 PIN 1 GND 1 INDICATOR 12 GND RFIN 2 11 RFOUT ADF5002 GND 3 10 RFOUT TOP VIEW GND 4 (Not to Scale) 9 GND 5 6 7 8 D C E D N N C N G G NOTES 1. NC = NO CONNECT.
02
2. THE EXPOSED PADDLE MUST BE
0 3-
CONNECTED TO GND.
75 08 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 3, 4, 5, 8, 9, GND RF Ground. All ground pins should be tied together. 12, 13, 16 2 RFIN Single-Ended 50 Ω Input to the RF Prescaler. This pin is ac-coupled internally via a 3 pF capacitor. 6 NC No Connect. This pin can be left unconnected. 7 CE Chip Enable. This pin is active high. When CE is brought low, the part enters power-down mode. If this functionality is not required, the pin can be left unconnected because it is pulled up internally through a weak pull-up resistor. 10 RFOUT Divided-Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an ac-coupling capacitor of 1 pF. 11 RFOUT Complementary Divided-Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an ac-coupling capacitor of 1 pF. 14 VDD2 Voltage Supply for the Output Stage. This pin should be decoupled to ground with a 0.1 μF capacitor in parallel with a 10 pF capacitor and can be tied directly to VDD1. 15 VDD1 Voltage Supply for the Input Stage and Divider Block. This pin should be decoupled to ground with a 0.1 μF capacitor in parallel with a 10 pF capacitor. EPAD The LFCSP has an exposed paddle that must be connected to GND. Rev. 0 | Page 5 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EVALUATION BOARD PCB PCB MATERIAL STACK-UP BILL OF MATERIALS APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE