Datasheet LTC3766 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | High Efficiency, Secondary-Side Synchronous Forward Controller |
| Pages / Page | 62 / 9 — PIN FUNCTIONS (SSOP/QFN) FGD (Pin 20/Pin 17):. VAUX (Pin 24/Pin 21):. PT … |
| File Format / Size | PDF / 2.0 Mb |
| Document Language | English |
PIN FUNCTIONS (SSOP/QFN) FGD (Pin 20/Pin 17):. VAUX (Pin 24/Pin 21):. PT –, PT+ (Pin 25, 26/Pin 22, 23):
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Text Version of Document
LTC3766
PIN FUNCTIONS (SSOP/QFN) FGD (Pin 20/Pin 17):
Forward Gate Rising Edge Delay. A
VAUX (Pin 24/Pin 21):
Auxiliary Power Input. This is the resistor to GND sets the delay from PT+ rising to FG rising power input to an internal LDO that is connected to VCC. (and SG falling). This delay is used to optimize the dead Whenever VAUX is greater than 4.7V (or 8V for high voltage time between the turn-off of SG and the turn-on of the mode), this LDO will supply power to VCC, bypassing the primary-side MOSFET. In standalone mode (100k or 50k main linear regulator that is powered from VIN. See VAUX resistor on MODE), this dead time is set adaptively and Connection in the Applications Information section. Do the FGD pin can be grounded. See Setting the Gate Driver not exceed 16V on the VAUX pin. Delays in the Applications Information section.
PT –, PT+ (Pin 25, 26/Pin 22, 23):
Pulse Transformer Driver
NDRV (Pin 21/Pin 18):
Drive Output for the External Pass Outputs. For most applications, these connect to a pulse Device of the High Voltage Linear Regulator Controller. transformer through a series DC-blocking capacitor. The Connect to the base (NPN) or gate (MOSFET) of an exter- PWM information is multiplexed together with DC power nal N-type device. Tie to VCC pin if only using the internal and sent through the pulse transformer to the primary side. LDO (VAUX pin). The PWM signal is then decoded by the LTC3765 active
V
clamp forward controller and gate driver. In standalone
IN (Pin 22/Pin 19):
Connect to a higher voltage bias supply when using the linear regulator controller. The V mode (100k or 50k resistor on MODE), the PT+ pin has a IN pin supplies bias to the internal standby and monitoring standard PWM signal and may be directly connected to circuits, the linear regulator controller, and the differential the gate of a primary-side MOSFET, while a reference clock amplifier. Tie to V is generated on the PT– pin. AUX pin if only using the internal LDO.
SW (Pin 23/Pin 20):
Connect (Kelvin) to the drain of the
PGND (Pin 27/Pin 24):
Gate Driver Ground Pin. Connect to synchronous MOSFET. This input is used for adaptive power ground at the source of the synchronous MOSFET. shoot-through prevention and leading-edge blanking,
VCC (Pin 28/Pin 25):
Main VCC Input for All Driver and monitoring the high level SW node voltage and SG reverse- Control Circuitry. current protection. When SW is high, the voltage on this pin is internally measured for use in the inductor ripple cancellation and volt-second limit circuits. When SW is low and SG is high, this pin sources a small current and is used for SG reverse overcurrent protection. A resistor can be placed between the SW pin and the drain of the synchronous MOSFET to adjust the SG reverse-over cur- rent threshold. The SW pin is internally clamped to 50V. 3766fc For more information www.linear.com/LTC3766 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Applications Information Typical Applications Typical Applications Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS (SSOP/QFN) FGD (Pin 20/Pin 17):
Forward Gate Rising Edge Delay. A
VAUX (Pin 24/Pin 21):
Auxiliary Power Input. This is the resistor to GND sets the delay from PT+ rising to FG rising power input to an internal LDO that is connected to VCC. (and SG falling). This delay is used to optimize the dead Whenever VAUX is greater than 4.7V (or 8V for high voltage time between the turn-off of SG and the turn-on of the mode), this LDO will supply power to VCC, bypassing the primary-side MOSFET. In standalone mode (100k or 50k main linear regulator that is powered from VIN. See VAUX resistor on MODE), this dead time is set adaptively and Connection in the Applications Information section. Do the FGD pin can be grounded. See Setting the Gate Driver not exceed 16V on the VAUX pin. Delays in the Applications Information section.
PT –, PT+ (Pin 25, 26/Pin 22, 23):
Pulse Transformer Driver
NDRV (Pin 21/Pin 18):
Drive Output for the External Pass Outputs. For most applications, these connect to a pulse Device of the High Voltage Linear Regulator Controller. transformer through a series DC-blocking capacitor. The Connect to the base (NPN) or gate (MOSFET) of an exter- PWM information is multiplexed together with DC power nal N-type device. Tie to VCC pin if only using the internal and sent through the pulse transformer to the primary side. LDO (VAUX pin). The PWM signal is then decoded by the LTC3765 active
V
clamp forward controller and gate driver. In standalone
IN (Pin 22/Pin 19):
Connect to a higher voltage bias supply when using the linear regulator controller. The V mode (100k or 50k resistor on MODE), the PT+ pin has a IN pin supplies bias to the internal standby and monitoring standard PWM signal and may be directly connected to circuits, the linear regulator controller, and the differential the gate of a primary-side MOSFET, while a reference clock amplifier. Tie to V is generated on the PT– pin. AUX pin if only using the internal LDO.
SW (Pin 23/Pin 20):
Connect (Kelvin) to the drain of the
PGND (Pin 27/Pin 24):
Gate Driver Ground Pin. Connect to synchronous MOSFET. This input is used for adaptive power ground at the source of the synchronous MOSFET. shoot-through prevention and leading-edge blanking,
VCC (Pin 28/Pin 25):
Main VCC Input for All Driver and monitoring the high level SW node voltage and SG reverse- Control Circuitry. current protection. When SW is high, the voltage on this pin is internally measured for use in the inductor ripple cancellation and volt-second limit circuits. When SW is low and SG is high, this pin sources a small current and is used for SG reverse overcurrent protection. A resistor can be placed between the SW pin and the drain of the synchronous MOSFET to adjust the SG reverse-over cur- rent threshold. The SW pin is internally clamped to 50V. 3766fc For more information www.linear.com/LTC3766 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Applications Information Typical Applications Typical Applications Typical Applications Package Description Revision History Typical Application Related Parts
