Datasheet LT3581 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 3.3A Boost/Inverting DC/DC Converter with Fault Protection |
| Pages / Page | 36 / 7 — PIN FUNCTIONS (DFN/MSOP). FB (Pin 1/Pin 1):. CLKOUT (Pin 10/Pin 12):. VC … |
| File Format / Size | PDF / 472 Kb |
| Document Language | English |
PIN FUNCTIONS (DFN/MSOP). FB (Pin 1/Pin 1):. CLKOUT (Pin 10/Pin 12):. VC (Pin 2/Pin 2):. SHDN (Pin 11/Pin 13):
Model Line for this Datasheet
Text Version of Document
LT3581
PIN FUNCTIONS (DFN/MSOP) FB (Pin 1/Pin 1):
Positive and Negative Feedback Pin. For
CLKOUT (Pin 10/Pin 12):
Clock Output Pin. Use this pin a Boost or Inverting Converter, tie a resistor from the FB to synchronize one or more other compatible switching pin to VOUT according to the following equations: regulator ICs to the LT3581. The clock that this pin outputs runs at the same frequency as the internal oscillator of the V R OUT – 1.215V FB = part or as the SYNC pin. CLKOUT may also be used as a 83.3•10–6 ;Boost or SEPIC Converter temperature monitor since the CLKOUT pin’s duty cycle |V varies linearly with the part’s junction temperature. Note R OUT | + 9mV FB = that the CLKOUT pin is only meant to drive capacitive 83.3•10–6 ;InvertingConverter loads up to 50pF.
VC (Pin 2/Pin 2):
Error Amplifier Output Pin. Tie external
SHDN (Pin 11/Pin 13):
Shutdown Pin. In conjunction com pensation network to this pin. with the UVLO (undervoltage lockout) circuit, this pin is
GATE (Pin 3/Pin 3):
PMOS Gate Drive Pin. The GATE pin used to enable/disable the chip and restart the soft-start is a pull-down current source, used to drive the gate of sequence. Drive below 300mV to disable the chip. Drive an external PMOS for output short circuit protection or above 1.33V (typical) to activate the chip and restart the output disconnect. The GATE pin current increases linearly soft-start sequence. Do not float this pin. with the SS pin’s voltage, with a maximum pull-down
RT (Pin 12/Pin 14):
Timing Resistor Pin. Adjusts the current of 933µA at SS voltages exceeding 500mV. Note LT3581’s switching frequency. Place a resistor from this that if the SS voltage is greater than 500mV and the GATE pin to ground to set the frequency to a fixed free running pin voltage is less than 2V, then the GATE pin looks like level. Do not float this pin. a 2kΩ impedance to ground. See the Appendix for more information.
SS (Pin 13/Pin 15):
Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged
FAULT (Pin 4/Pin 4):
Fault Indication Pin. This active low, by a (nominally) 250k resistor to about 2.1V. During a bidirectional pin can either be pulled low (below 750mV) fault, the SS pin will be slowly charged up and eventually by an external source, or internally by the chip to indicate a discharged as part of a timeout sequence (see the State fault. When pulled low, this pin causes the power switches Diagram for more information on the SS pin’s role during to turn off, the GATE pin to become high impedance, the a fault event). CLKOUT pin to become disabled, and the SS pin to go through a charge/discharge sequence. The end/absence
SYNC (Pin 14/Pin 16):
To synchronize the switching of a fault is indicated when the voltage on this pin exceeds frequency to an outside clock, simply drive this pin with 1V. A pull-up resistor or current source is needed on this a clock. The high voltage level of the clock must exceed pin to pull it above 1V in the absence of a fault. 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running
VIN (Pin 5/Pin 5):
Input Supply Pin. Must be locally by- clock. See the Applications Information section for more passed. information.
SW1 (Pins 6, 7/Pins 6,7, 8):
Master Switch Pin. This is the
GND (Exposed Pad Pin 15/Exposed Pad Pin 17):
Ground. collector of the internal master NPN power switch. Exposed pad must be soldered directly to local ground Minimize the metal trace area connected to this pin to plane. minimize EMI.
SW2 (Pins 8, 9/Pins 9, 10, 11):
Slave Switch Pin. This is the collector of the internal slave NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI. 3581fb For more information www.linear.com/LT3581 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram State Diagram Operation Applications Information Appendix Typical Applications Typical Application Related Parts
PIN FUNCTIONS (DFN/MSOP) FB (Pin 1/Pin 1):
Positive and Negative Feedback Pin. For
CLKOUT (Pin 10/Pin 12):
Clock Output Pin. Use this pin a Boost or Inverting Converter, tie a resistor from the FB to synchronize one or more other compatible switching pin to VOUT according to the following equations: regulator ICs to the LT3581. The clock that this pin outputs runs at the same frequency as the internal oscillator of the V R OUT – 1.215V FB = part or as the SYNC pin. CLKOUT may also be used as a 83.3•10–6 ;Boost or SEPIC Converter temperature monitor since the CLKOUT pin’s duty cycle |V varies linearly with the part’s junction temperature. Note R OUT | + 9mV FB = that the CLKOUT pin is only meant to drive capacitive 83.3•10–6 ;InvertingConverter loads up to 50pF.
VC (Pin 2/Pin 2):
Error Amplifier Output Pin. Tie external
SHDN (Pin 11/Pin 13):
Shutdown Pin. In conjunction com pensation network to this pin. with the UVLO (undervoltage lockout) circuit, this pin is
GATE (Pin 3/Pin 3):
PMOS Gate Drive Pin. The GATE pin used to enable/disable the chip and restart the soft-start is a pull-down current source, used to drive the gate of sequence. Drive below 300mV to disable the chip. Drive an external PMOS for output short circuit protection or above 1.33V (typical) to activate the chip and restart the output disconnect. The GATE pin current increases linearly soft-start sequence. Do not float this pin. with the SS pin’s voltage, with a maximum pull-down
RT (Pin 12/Pin 14):
Timing Resistor Pin. Adjusts the current of 933µA at SS voltages exceeding 500mV. Note LT3581’s switching frequency. Place a resistor from this that if the SS voltage is greater than 500mV and the GATE pin to ground to set the frequency to a fixed free running pin voltage is less than 2V, then the GATE pin looks like level. Do not float this pin. a 2kΩ impedance to ground. See the Appendix for more information.
SS (Pin 13/Pin 15):
Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged
FAULT (Pin 4/Pin 4):
Fault Indication Pin. This active low, by a (nominally) 250k resistor to about 2.1V. During a bidirectional pin can either be pulled low (below 750mV) fault, the SS pin will be slowly charged up and eventually by an external source, or internally by the chip to indicate a discharged as part of a timeout sequence (see the State fault. When pulled low, this pin causes the power switches Diagram for more information on the SS pin’s role during to turn off, the GATE pin to become high impedance, the a fault event). CLKOUT pin to become disabled, and the SS pin to go through a charge/discharge sequence. The end/absence
SYNC (Pin 14/Pin 16):
To synchronize the switching of a fault is indicated when the voltage on this pin exceeds frequency to an outside clock, simply drive this pin with 1V. A pull-up resistor or current source is needed on this a clock. The high voltage level of the clock must exceed pin to pull it above 1V in the absence of a fault. 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running
VIN (Pin 5/Pin 5):
Input Supply Pin. Must be locally by- clock. See the Applications Information section for more passed. information.
SW1 (Pins 6, 7/Pins 6,7, 8):
Master Switch Pin. This is the
GND (Exposed Pad Pin 15/Exposed Pad Pin 17):
Ground. collector of the internal master NPN power switch. Exposed pad must be soldered directly to local ground Minimize the metal trace area connected to this pin to plane. minimize EMI.
SW2 (Pins 8, 9/Pins 9, 10, 11):
Slave Switch Pin. This is the collector of the internal slave NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI. 3581fb For more information www.linear.com/LT3581 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram State Diagram Operation Applications Information Appendix Typical Applications Typical Application Related Parts
