Datasheet LTC3783 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | PWM LED Driver and Boost, Flyback and SEPIC Controller |
| Pages / Page | 24 / 7 — PIN FUNCTIONS. FBN (Pin 1):. PWMIN (Pin 7):. PWMOUT (Pin 8):. GATE (Pin … |
| File Format / Size | PDF / 311 Kb |
| Document Language | English |
PIN FUNCTIONS. FBN (Pin 1):. PWMIN (Pin 7):. PWMOUT (Pin 8):. GATE (Pin 9):. INTVCC (Pin 10):. FBP (Pin 2):. IN (Pin 11):
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Text Version of Document
LTC3783
PIN FUNCTIONS FBN (Pin 1):
Error Amplifier Inverting Input/Negative Cur-
PWMIN (Pin 7):
PWM Gate Driver Input. Internal 100k rent Sense Pin. In voltage mode (VFBP ≤ VVREF), this pin pull-up resistor. While PWMIN is low, PWMOUT is low, senses feedback voltage from either the external resistor GATE stops switching and the external ITH network is divider across VOUT for output voltage regulation, or the disconnected, saving the ITH state. grounded sense resistor under the load for output current
PWMOUT (Pin 8):
PWM Gate Driver Output. Used for con- regulation. In constant current/constant voltage mode stant current dimming (LED load) or for output disconnect (VFBP > 2.5V), connect this pin to the negative side of the (step-up power supply). current-regulating resistor. Nominal voltage for this pin in regulation is either VFBP or (VFBP – 100mV) for VILIM = 1.23V,
GATE (Pin 9):
Main Gate Driver Output for the Boost depending on operational mode (voltage or constant cur- Converter. rent/constant voltage) set by the voltage at VFBP.
INTVCC (Pin 10):
Internal 7V Regulator Output. The main
FBP (Pin 2):
Error Amplifier Noninverting Input/Positive and PWM gate drivers and control circuits are powered Current Sense Pin. This pin voltage determines the control from this voltage. Decouple this pin locally to the IC ground loop’s feedback mode (voltage or constant current/constant with a minimum of 4.7µF low ESR ceramic capacitor. voltage), the threshold of which is approximately 2V. In
V
voltage mode (V
IN (Pin 11):
Main Supply Pin. Must be closely decoupled FBP ≤ VREF), this pin represents the desired to ground. voltage which the regulated loop will cause FBN to follow. In constant current/constant voltage mode (V
SENSE (Pin 12):
Current Sense Input for the Control Loop. FBP > 2.5V), connect this pin to the positive side of the load current- Connect this pin to the drain of the main power MOSFET sensing resistor. The acceptable input ranges for this pin for VDS sensing and highest efficiency for VSENSE ≤ 36V. are 0V to 1.23V (voltage mode) and 2.5V to 36V (constant Alternatively, the SENSE pin may be connected to a resistor current/constant voltage mode). in the source of the main power MOSFET. Internal leading- edge blanking is provided for both sensing methods.
ILIM(Pin 3):
Current Limit Pin. Sets current sense resis- tor offset voltage (V
SS (Pin 13):
Soft-Start Pin. Provides a 50µA pull-up current, FBP – VFBN) in constant current mode regulation (i.e., when V enabled and reset by RUN, which charges an optional external FBP > 2.5V). Offset voltage is 100mV when V capacitor. This voltage ramp translates into a corresponding ILIM = 1.23V and decreases proportionally with VILIM. Nominal voltage range for this pin is 0.1V to 1.23V. current limit ramp through the main MOSFET.
V OV/FB (Pin 14):
Overvoltage Pin/Voltage Feedback Pin.
REF (Pin 4):
Reference Voltage Pin. Provides a buffered version of the internal bandgap voltage, which can be In voltage mode (VFBP ≤ VREF), this input, connected to connected to FBP either directly or with attenuation. VOUT through a resistor network, sets the output voltage Nominal voltage for this pin is 1.23V. This pin should at which GATE switching is disabled in order to prevent never be bypassed by a capacitor to GND. Instead, a 10k an overvoltage situation. Nominal threshold voltage for resistor to GND should be used to lower pin impedance the OV pin is 1.32V (VREF + 7%) with 20mV hysteresis. In in noisy systems. current/voltage mode (VFBP > 2.5V), this pin senses VOUT through a resistor divider and brings the loop into voltage
FREQ (Pin 5):
A resistor from the FREQ pin to ground regulation such that pin voltage approaches V programs the operating frequency of the chip. The nominal REF = 1.23V, provided the loop is not regulating the load current (e.g., voltage at the FREQ pin is 0.615V. [VFBP – VFBN] < 100mV for ILIM = 1.23V).
SYNC (Pin 6):
This input allows for synchronizing the op- erating frequency to an external clock and has an internal 100k pull-down resistor. 3783fb 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Block Diagram Operation Package Description Related Parts
PIN FUNCTIONS FBN (Pin 1):
Error Amplifier Inverting Input/Negative Cur-
PWMIN (Pin 7):
PWM Gate Driver Input. Internal 100k rent Sense Pin. In voltage mode (VFBP ≤ VVREF), this pin pull-up resistor. While PWMIN is low, PWMOUT is low, senses feedback voltage from either the external resistor GATE stops switching and the external ITH network is divider across VOUT for output voltage regulation, or the disconnected, saving the ITH state. grounded sense resistor under the load for output current
PWMOUT (Pin 8):
PWM Gate Driver Output. Used for con- regulation. In constant current/constant voltage mode stant current dimming (LED load) or for output disconnect (VFBP > 2.5V), connect this pin to the negative side of the (step-up power supply). current-regulating resistor. Nominal voltage for this pin in regulation is either VFBP or (VFBP – 100mV) for VILIM = 1.23V,
GATE (Pin 9):
Main Gate Driver Output for the Boost depending on operational mode (voltage or constant cur- Converter. rent/constant voltage) set by the voltage at VFBP.
INTVCC (Pin 10):
Internal 7V Regulator Output. The main
FBP (Pin 2):
Error Amplifier Noninverting Input/Positive and PWM gate drivers and control circuits are powered Current Sense Pin. This pin voltage determines the control from this voltage. Decouple this pin locally to the IC ground loop’s feedback mode (voltage or constant current/constant with a minimum of 4.7µF low ESR ceramic capacitor. voltage), the threshold of which is approximately 2V. In
V
voltage mode (V
IN (Pin 11):
Main Supply Pin. Must be closely decoupled FBP ≤ VREF), this pin represents the desired to ground. voltage which the regulated loop will cause FBN to follow. In constant current/constant voltage mode (V
SENSE (Pin 12):
Current Sense Input for the Control Loop. FBP > 2.5V), connect this pin to the positive side of the load current- Connect this pin to the drain of the main power MOSFET sensing resistor. The acceptable input ranges for this pin for VDS sensing and highest efficiency for VSENSE ≤ 36V. are 0V to 1.23V (voltage mode) and 2.5V to 36V (constant Alternatively, the SENSE pin may be connected to a resistor current/constant voltage mode). in the source of the main power MOSFET. Internal leading- edge blanking is provided for both sensing methods.
ILIM(Pin 3):
Current Limit Pin. Sets current sense resis- tor offset voltage (V
SS (Pin 13):
Soft-Start Pin. Provides a 50µA pull-up current, FBP – VFBN) in constant current mode regulation (i.e., when V enabled and reset by RUN, which charges an optional external FBP > 2.5V). Offset voltage is 100mV when V capacitor. This voltage ramp translates into a corresponding ILIM = 1.23V and decreases proportionally with VILIM. Nominal voltage range for this pin is 0.1V to 1.23V. current limit ramp through the main MOSFET.
V OV/FB (Pin 14):
Overvoltage Pin/Voltage Feedback Pin.
REF (Pin 4):
Reference Voltage Pin. Provides a buffered version of the internal bandgap voltage, which can be In voltage mode (VFBP ≤ VREF), this input, connected to connected to FBP either directly or with attenuation. VOUT through a resistor network, sets the output voltage Nominal voltage for this pin is 1.23V. This pin should at which GATE switching is disabled in order to prevent never be bypassed by a capacitor to GND. Instead, a 10k an overvoltage situation. Nominal threshold voltage for resistor to GND should be used to lower pin impedance the OV pin is 1.32V (VREF + 7%) with 20mV hysteresis. In in noisy systems. current/voltage mode (VFBP > 2.5V), this pin senses VOUT through a resistor divider and brings the loop into voltage
FREQ (Pin 5):
A resistor from the FREQ pin to ground regulation such that pin voltage approaches V programs the operating frequency of the chip. The nominal REF = 1.23V, provided the loop is not regulating the load current (e.g., voltage at the FREQ pin is 0.615V. [VFBP – VFBN] < 100mV for ILIM = 1.23V).
SYNC (Pin 6):
This input allows for synchronizing the op- erating frequency to an external clock and has an internal 100k pull-down resistor. 3783fb 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Block Diagram Operation Package Description Related Parts
