Datasheet LT3750 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Capacitor Charger Controller |
| Pages / Page | 16 / 4 — PI FU CTIO S. VTRANS (Pin 1):. SOURCE (Pin 6):. GATE (Pin 7):. DONE (Pin … |
| File Format / Size | PDF / 228 Kb |
| Document Language | English |
PI FU CTIO S. VTRANS (Pin 1):. SOURCE (Pin 6):. GATE (Pin 7):. DONE (Pin 2):. RDCM (Pin 8):. CHARGE (Pin 3):. OUT (Pin 9):
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Text Version of Document
LT3750
U U U PI FU CTIO S VTRANS (Pin 1):
Transformer Supply Pin. Powers the
SOURCE (Pin 6):
Source Pin. Senses NMOS drain current. primary coil of the transformer as well as internal circuitry Connect NMOS source terminal and current sense resistor that performs boundary mode detection. Bypass at the pin to this pin. The current limit is 78mV/RSENSE. with a 1µF to 10µF capacitor. Bypass the primary winding
GATE (Pin 7):
Gate Pin. Connect NMOS gate terminal to of the transformer with a large capacitor. this pin. Internal gate driver will drive voltage to within
DONE (Pin 2):
Open Collector Indication Pin. When target VCC – 2V during each switching cycle. output voltage is reached, an NPN transistor turns on.
RDCM (Pin 8):
Discontinuous Mode Sense Pin. Senses Requires a pull-up resistor or current source. Any fault when current in transformer has decayed to zero and ini- conditions such as thermal shutdown or undervoltage tiates a new charge cycle if output voltage target has not lockout will also turn on the NPN. been reached. Place a resistor between this pin and the drain
CHARGE (Pin 3):
Charge Pin. Initiates a new charge cycle of the NMOS. A good choice is a 43k, 5% resistor. when brought high or discontinues charging and puts part
RV
into shutdown when low. To properly enable the device, a
OUT (Pin 9):
Output Voltage VI Converter Pin. Develops a current proportional to output capacitor voltage. Con- step input with a minimum ramp rate of 1V/µs is required. nect a resistor between this pin and the drain of the NMOS. Drive to 1.1V or higher to enable the device; drive below 0.2V to disable the device.
RBG (Pin 10):
Output Voltage Sense Pin. Senses the voltage across the RBG resistor, which is proportional to
VCC (Pin 4):
Input Supply Pin. Bypass locally with a the current flowing into the R ceramic capacitor. A 1µF to 10µF ceramic capacitor should VOUT pin. When voltage equals 1.24V, charging is disabled and DONE pin goes be sufficient for most applications. low. Connect a resistor (2.5k or less is recommended)
GND (Pin 5):
Ground Pin. Connect directly to local ground from this pin to GND. A 2.49k, 1% resistor is a good plane. choice. 3750fa 4
U U U PI FU CTIO S VTRANS (Pin 1):
Transformer Supply Pin. Powers the
SOURCE (Pin 6):
Source Pin. Senses NMOS drain current. primary coil of the transformer as well as internal circuitry Connect NMOS source terminal and current sense resistor that performs boundary mode detection. Bypass at the pin to this pin. The current limit is 78mV/RSENSE. with a 1µF to 10µF capacitor. Bypass the primary winding
GATE (Pin 7):
Gate Pin. Connect NMOS gate terminal to of the transformer with a large capacitor. this pin. Internal gate driver will drive voltage to within
DONE (Pin 2):
Open Collector Indication Pin. When target VCC – 2V during each switching cycle. output voltage is reached, an NPN transistor turns on.
RDCM (Pin 8):
Discontinuous Mode Sense Pin. Senses Requires a pull-up resistor or current source. Any fault when current in transformer has decayed to zero and ini- conditions such as thermal shutdown or undervoltage tiates a new charge cycle if output voltage target has not lockout will also turn on the NPN. been reached. Place a resistor between this pin and the drain
CHARGE (Pin 3):
Charge Pin. Initiates a new charge cycle of the NMOS. A good choice is a 43k, 5% resistor. when brought high or discontinues charging and puts part
RV
into shutdown when low. To properly enable the device, a
OUT (Pin 9):
Output Voltage VI Converter Pin. Develops a current proportional to output capacitor voltage. Con- step input with a minimum ramp rate of 1V/µs is required. nect a resistor between this pin and the drain of the NMOS. Drive to 1.1V or higher to enable the device; drive below 0.2V to disable the device.
RBG (Pin 10):
Output Voltage Sense Pin. Senses the voltage across the RBG resistor, which is proportional to
VCC (Pin 4):
Input Supply Pin. Bypass locally with a the current flowing into the R ceramic capacitor. A 1µF to 10µF ceramic capacitor should VOUT pin. When voltage equals 1.24V, charging is disabled and DONE pin goes be sufficient for most applications. low. Connect a resistor (2.5k or less is recommended)
GND (Pin 5):
Ground Pin. Connect directly to local ground from this pin to GND. A 2.49k, 1% resistor is a good plane. choice. 3750fa 4
