Datasheet LTC3721-1 (Analog Devices) - 6

LTC3721-1
U U PI DESCRIPTIO S (GN Package/UF Package) VREF (Pin 1/Pin 15):
Output of the 5.0V Reference. VREF is GND as practical for best performance. For the 4mm × capable of supplying up to 18mA to external circuitry. VREF 4mm QFN package only, the internal power (PGND) and should be decoupled to GND with a 1µF ceramic capacitor. signal (SGND) buses are connected separately to pins 4 and 5 respectively, and the exposed pad must be soldered
DRVB (Pin 4/Pin 1):
High Speed 1.5A Sink, 1A Source to PCB ground. Totem Pole MOSFET Driver. Connect to gate of external push-pull MOSFET with as short a PCB trace as practical
CT (Pin 8/Pin 6):
Timing Capacitor for the Oscillator. Use to preserve drive signal integrity. A low value resistor a ±5% or better low ESR ceramic capacitor for best connected between DRVA and the MOSFET gate is op- results. CT ramp amplitude is 2.35V peak-to-peak tional and will improve the gate drive signal quality if the (typical). PCB trace from the driver to the MOSFET cannot be made
DPRG (Pin 9/Pin 8):
Programming Input for Push-Pull short. Dead-Time. Connect a resistor between DPRG and VREF to
VCC (Pin 5/Pin 2):
Supply Voltage Input to the LTC3721-1 program the dead-time. The nominal voltage on DPRG is and 10.25V Shunt Regulator. The chip is enabled after VCC 2V. has risen high enough to allow the VCC shunt regulator to
CS (Pin 10/Pin 9):
Input to Pulse-by-Pulse and Overload conduct current and the UVLO comparator threshold is Current Limit Comparators, Output of Slope Compensa- exceeded. Once the VCC shunt regulator has turned on, tion Circuitry. The pulse-by-pulse comparator has a nomi- VCC can drop to as low as 6V (typical) and maintain nal 300mV threshold, while the overload comparator has operation. Bypass VCC to GND with a high quality 1µF or a nominal 600mV threshold. An internal switch discharges larger ceramic capacitor to supply the transient currents CS to GND after every timing period. Slope compensation caused by the high speed switching and capacitive loads current flows out of CS during the PWM period. presented by the on chip totem pole drivers. An external resistor connected from CS to the external
DRVA (Pin 6/Pin 3):
High Speed 1.5A Sink, 1A Source current sense resistor programs the amount of slope Totem Pole MOSFET Driver. Connect to gate of external compensation. push-pull MOSFET with as short a PCB trace as practical
COMP (Pin 11/Pin 10):
Error Amplifier Output, Inverting to preserve drive signal integrity. A low value resistor Input to Phase Modulator. connected between DRVA and the MOSFET gate is op- tional and will improve the gate drive signal quality if the
RLEB (Pin 12/Pin 11):
Timing Resistor for Leading Edge PCB trace from the driver to the MOSFET cannot be made Blanking. Use a 10k to 100k resistor connected between short. RLEB and GND to program from 40ns to 310ns of leading edge blanking of the current sense signal on CS for the
GND (Pin 7/Pin 4, Pin 5, Pin 17):
All circuits in the LTC3721-1. A ±1% tolerance resistor is recommended. LTC3721-1 are referenced to GND. Use of a ground plane The nominal voltage on R is highly recommended. V LEB is 2V. If leading edge blank- IN and VREF bypass capacitors ing is not required, tie R must be terminated with a star configuration as close to LEB to VREF to disable. sn37211 37211fs 6