Datasheet LT1680 (Analog Devices) - 10

LT1680
U U W U APPLICATIO S I FOR ATIO
200 capacitor CSS, the start up delay time to full available CCT = 0.68nF 180 average current will be: CCT = 1nF 160 tSS = (1.5)(105)(CSS) CCT = 1.5nF 140 CCT = 2.2nF 120
Shutdown Function—Input Undervoltage Detect
100
and Threshold Hysteresis
80 The LT1680 RUN/SHDN pin uses a bandgap generated OSCILLATOR FREQUENCY (kHz) 60 reference threshold of about 1.25V. This precision thresh- old allows use of the RUN/SHDN pin for both logic-level 40 3 7 11 15 19 23 27 31 35 39 43 47 shutdown applications and analog monitoring applica- TIMING RESISTOR (kΩ) tions such as power supply sequencing. 1680 F02 Because an LT1680 controlled converter is a power trans-
Figure 2. Operating Frequency vs RCT, CCT
fer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourc-
Average Current Limit
ing capabilities of that supply, causing the system to lock- The average current limit function is implemented using up in an undervoltage state. Input supply start-up protection an external capacitor (CAVG) connected either from the can be achieved by enabling the RUN/SHDN pin using a IAVG pin to the VC pin or from the IAVG pin to SGND. This resistor divider from the input supply to ground. Setting capacitor forms a single-pole integrator with the 50kΩ the divider output to 1.25V when the supply is almost fully output impedance of the IAVG pin. Precise integration enabled prevents the LT1680 regulator from drawing large frequencies can be determined using a ground reference currents until the input supply is able to supply the integration capacitor using the relation: required power. f–3dB = (3.2)(10–6)/CAVG If additional hysteresis is desired for the enable function, Connecting a capacitor from the I an external feedback resistor can be used from the LT1680 AVG pin to the VC pin uses an internal gain block to form an active integrator circuit, regulator output. If connection to the regulator output is minimizing the required capacitance for stable operation. not desired, the 5VREF internal supply pin can be used. A typical value for this integration capacitor is 220pF from Figure 3 shows an input supply sequencing configuration I on a 24V input converter. This configuration yields an AVG to VC. enable condition of 90% VIN (~ 21.5V) with about 10% Shorting the IAVG pin to SGND will disable the average threshold hysteresis. current limit function. The shutdown function can be disabled by connecting the
Soft Start Programming
RUN/SHDN pin to the 12VIN rail. This pin is internally The current control pin (V V C) limits sensed inductor current IN 24V to zero at voltages less than a transistor VBE, to full average current limit at V 160k C = VBE + 1.8V. This generates a 1.8V full 16 regulation range for average load current. An internal 5VREF 390k voltage clamp forces the V LT1680 C pin to a VBE – 100mV above 11 RUN/SHDN the SS pin voltage. This 100mV “dead zone” assures 0% 10k 1680 F03 duty cycle operation at the start of the soft start cycle or when the soft start pin is pulled to ground. Given the typical soft start current of 8µA and a soft start timing
Figure 3. Input Supply Sequencing Programming
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