Datasheet ATtiny2313, ATtiny2313V (Atmel) - 173

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ATtiny2313 Serial Programming
When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK.
Algorithm
When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See Figure 79, Figure 80 and Table 78 for timing details. To program and verify the ATtiny2313 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 77 on page 174): 1. Power-up sequence: Apply power between V and GND while RESET and SCK are set to “0”. In some sys- CC tems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchro- nization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least t before WD_FLASH issuing the next page. (See Table 76 on page 174.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5.
A:
The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least t before issuing the next byte. (See Table 76 on page 174.) WD_EEPROM In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B:
The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 5 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least t before issuing the next page (See Table WD_EEPROM 76 on page 174). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the con- tent at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn V power off. CC
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2543M–AVR–10/16 Document Outline Features Pin Configurations Overview Block Diagram Pin Descriptions VCC GND Port A (PA2..PA0) Port B (PB7..PB0) Port D (PD6..PD0) RESET XTAL1 XTAL2 General Information Resources Code Examples Data Retention AVR CPU Core Introduction Architectural Overview ALU – Arithmetic Logic Unit Status Register General Purpose Register File The X-register, Y- register, and Z-register Stack Pointer Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR ATtiny2313 Memories In-System Reprogrammable Flash Program Memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register The EEPROM Data Register – EEDR The EEPROM Control Register – EECR Atomic Byte Programming Split Byte Programming Erase Write Preventing EEPROM Corruption I/O Memory General Purpose I/O Registers General Purpose I/O Register 2 – GPIOR2 General Purpose I/O Register 1 – GPIOR1 General Purpose I/O Register 0 – GPIOR0 System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH Clock Sources Default Clock Source Crystal Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock 128 kHz Internal Oscillator System Clock Prescalar CLKPR – Clock Prescale Register Power Management and Sleep Modes MCU Control Register – MCUCR Idle Mode Power-down Mode Standby Mode Minimizing Power Consumption Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register – MCUSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer Watchdog Timer Control and Status Register - WDTCSR Interrupts Interrupt Vectors in ATtiny2313 I/O-Ports Introduction Ports as General Digital I/O Configuring the Pin Toggling the Pin Switching Between Input and Output Reading the Pin Value Digital Input Enable and Sleep Modes Alternate Port Functions MCU Control Register – MCUCR Alternate Functions of Port A Alternate Functions of Port B Alternate Functions of Port D Register Description for I/O-Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND External Interrupts Pin Change Interrupt Timing MCU Control Register – MCUCR General Interrupt Mask Register – GIMSK External Interrupt Flag Register – EIFR Pin Change Mask Register – PCMSK 8-bit Timer/Counter0 with PWM Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register A – TCCR0A Timer/Counter Control Register B – TCCR0B Timer/Counter Register – TCNT0 Output Compare Register A – OCR0A Output Compare Register B – OCR0B Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source General Timer/Counter Control Register – GTCCR 16-bit Timer/Counter1 Overview Registers Definitions Compatibility Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Trigger Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 Control Register C – TCCR1C Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B - OCR1BH and OCR1BL Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR USART Overview AVR USART vs. AVR UART – Compatibility Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2X) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bit Sending Frames with 9 Data Bit Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Multi-processor Communication Mode Using MPCM USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA USART Control and Status Register B – UCSRB USART Control and Status Register C – UCSRC USART Baud Rate Registers – UBRRL and UBRRH Examples of Baud Rate Setting Universal Serial Interface – USI Overview Functional Descriptions Three-wire Mode SPI Master Operation Example SPI Slave Operation Example Two-wire Mode Start Condition Detector Alternative USI Usage Half-duplex Asynchronous Data Transfer 4-bit Counter 12-bit Timer/Counter Edge Triggered External Interrupt Software Interrupt USI Register Descriptions USI Data Register – USIDR USI Status Register – USISR USI Control Register – USICR Analog Comparator Analog Comparator Control and Status Register – ACSR Digital Input Disable Register – DIDR debugWIRE On- chip Debug System Features Overview Physical Interface Software Break Points Limitations of debugWIRE debugWIRE Related Register in I/O Memory debugWire Data Register – DWDR Self- Programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) Performing a Page Write Addressing the Flash During Self- Programming Store Program Memory Control and Status Register – SPMCSR EEPROM Write Prevents Writing to SPMCSR Reading the Fuse and Lock Bits from Software Preventing Flash Corruption Programming Time for Flash when Using SPM Memory Programming Program And Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Page Size Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Serial Programming Pin Mapping Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Extended Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics System and Reset Characteristics External Clock Drive Waveforms External Clock Drive Maximum Speed vs. VCC ATtiny2313 Typical Characteristics Active Supply Current Idle Supply Current Power-down Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis BOD Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulsewidth Register Summary Instruction Set Summary Ordering Information Packaging Information 20P3 20S 20M1 Errata ATtiny2313 Rev C ATtiny2313 Rev B ATtiny2313 Rev A Datasheet Revision History Rev. 2543M – 10/16 Rev. 2543L – 08/10 Rev. 2543K – 03/10 Rev. 2543J – 11/09 Rev. 2543I – 04/06 Rev. 2543H – 02/05 Rev. 2543G – 10/04 Rev. 2543F – 08/04 Rev. 2543E – 04/04 Rev. 2543D – 03/04 Rev. 2543C – 12/03 Rev. 2543B – 09/03 Rev. 2543A