Datasheet ATtiny26, ATtiny26L (Atmel) - 8

link to page 8 concept enables instructions to be executed in every clock cycle. The program memory is In- System programmable Flash memory. With the relative jump and relative call instructions, the whole address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit Stack Pointer SP is read/write accessible in the I/O space. For programs written in C, the stack size must be declared in the linker file. Refer to the C user guide for more information. The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, Timer/Counters, and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All the different interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the program memory. The different inter- rupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
General Purpose
Figure 3 shows the structure of the 32 general purpose working registers in the CPU.
Register File Figure 3.
AVR CPU General Purpose Working Registers 7 0 Addr. R0 $00 R1 $01 R2 $02 … R13 $0D General R14 $0E Purpose R15 $0F Working R16 $10 Registers R17 $11 … R26 $1A X-register Low Byte R27 $1B X-register High Byte R28 $1C Y-register Low Byte R29 $1D Y-register High Byte R30 $1E Z-register Low Byte R31 $1F Z-register High Byte
8 ATtiny26(L)
1477K–AVR–08/10 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND AVCC Port A (PA7..PA0) Port B (PB7..PB0) XTAL1 XTAL2 General Information Resources Code Examples AVR CPU Core Architectural Overview General Purpose Register File X-register, Y-register, and Z-register ALU – Arithmetic Logic Unit Status Register – SREG Stack Pointer – SP Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post-increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL Memories In-System Programmable Flash Program Memory SRAM Data Memory EEPROM Data Memory EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR EEPROM Write During Power-down Sleep Mode Preventing EEPROM Corruption I/O Memory System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH ADC Clock – clkADC Internal PLL for Fast Peripheral Clock Generation – clkPCK Clock Sources Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator External RC Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock High Frequency PLL Clock – PLLCLK System Control and Reset Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register – MCUSR Power Management and Sleep Modes MCU Control Register – MCUCR Idle Mode ADC Noise Reduction Mode Power-down Mode Standby Mode Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins I/O Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected Pins Alternate Port Functions MCU Control Register – MCUCR Alternate Functions of Port A Alternate Functions Of Port B Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Interrupts Interrupt Vectors Interrupt Handling Interrupt Response Time General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupt Pin Change Interrupt Timer/Counters Timer/Counter0 Prescaler Timer/Counter1 Prescaler 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer/Counter0 – TCNT0 8-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1 Timer/Counter1 Output Compare RegisterA – OCR1A Timer/Counter1 Output Compare RegisterB – OCR1B Timer/Counter1 Output Compare RegisterC – OCR1C PLL Control and Status Register – PLLCSR Timer/Counter1 Initialization for Asynchronous Mode Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register – WDTCR Universal Serial Interface – USI Overview Register Descriptions USI Data Register – USIDR USI Status Register – USISR USI Control Register – USICR Functional Descriptions Three-wire Mode SPI Master Operation Example SPI Slave Operation Example Two-wire Mode Start Condition Detector Alternative USI Usage Half-duplex Asynchronous Data Transfer 4-bit Counter 12-bit Timer/Counter Edge Triggered External Interrupt Software Interrupt Analog Comparator Analog Comparator Control and Status Register – ACSR Analog to Digital Converter Features Operation Prescaling and Conversion Timing Changing Channel or Reference Selection ADC Noise Canceler Function ADC Conversion Result ADC Multiplexer Selection Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL and ADCH ADLAR = 0 ADLAR = 1 Scanning Multiple Channels ADC Noise Canceling Techniques Offset Compensation Schemes Memory Programming Program and Data Memory Lock Bits Fuse Bits Latching of Fuses Signature Bytes Calibration Byte Page Size Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading Serial Programming Pin Mapping SPI Serial Programming Algorithm Data Polling Flash Data Polling EEPROM Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive ADC Characteristics ATtiny26 Typical Characteristics Active Supply Current Idle Supply Current Power-down Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds and Hysteresis BOD Thresholds and Analog Comparator Offset Internal Oscillator Speed Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulsewidth Register Summary Instruction Set Summary Ordering Information Packaging Information 20P3 20S 32M1-A Errata ATtiny26 Rev. B/C/D Datasheet Revision History Rev. 1477K-08/10 Rev. 1477J-06/07 Rev. 1477I-05/06 Rev. 1477H-04/06 Rev. 1477G-03/05 Rev. 1477F-12/04 Rev. 1477E-10/03 Rev. 1477D-05/03 Rev. 1477C-09/02 Rev. 1477B-04/02 Rev. 1477A-03/02 Table of Contents