Datasheet ATtiny28L, ATtiny28V (Atmel) - 10
| Manufacturer | Atmel |
| Pages / Page | 81 / 10 — Memories. I/O Memory. Table 3. Address Hex. Name. Function. ATtiny28L/V |
| File Format / Size | PDF / 680 Kb |
| Document Language | English |
Memories. I/O Memory. Table 3. Address Hex. Name. Function. ATtiny28L/V
Model Line for this Datasheet
Text Version of Document
Memories I/O Memory
The I/O space definition of the ATtiny28 is shown in Table 3.
Table 3.
ATtiny28 I/O Space
Address Hex Name Function
$3F SREG Status Register $1B PORTA Data Register, Port A $1A PACR Port A Control Register $19 PINA Input Pins, Port A $16 PINB Input Pins, Port B $12 PORTD Data Register, Port D $11 DDRD Data Direction Register, Port D $10 PIND Input Pins, Port D $08 ACSR Analog Comparator Control and Status Register $07 MCUCS MCU Control and Status Register $06 ICR Interrupt Control Register $05 IFR Interrupt Flag Register $04 TCCR0 Timer/Counter0 Control Register $03 TCNT0 Timer/Counter0 (8-bit) $02 MODCR Modulation Control Register $01 WDTCR Watchdog Timer Control Register $00 OSCCAL Oscillator Calibration Register Note: Reserved and unused locations are not shown in the table. All ATtiny28 I/O and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general-pur- pose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set section for more details. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. The I/O and peripherals control registers are explained in the following sections.
10 ATtiny28L/V
1062F–AVR–07/06 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA3..PA0) Port B (PB7..PB0) Port D (PD7..PD0) XTAL1 XTAL2 RESET Architectural Overview ALU - Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File Status Register Status Register - SREG System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock External RC Oscillator Register Description Oscillator Calibration Register - OSCCAL Memories I/O Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction Memory Access and Instruction Execution Timing Flash Program Memory Sleep Modes Idle Mode Power-down Mode System Control and Reset Reset Sources Power-on Reset External Reset Watchdog Reset Register Description MCU Control and Status Register - MCUCS Interrupts Reset and Interrupt Interrupt Handling Interrupt Response Time External Interrupt Low-level Input Interrupt Register Description Interrupt Control Register - ICR Interrupt Flag Register - IFR I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 Port A Schematics Port B Port B as General Digital Input Alternate Functions of Port B Port B Schematics Port D Port D as General Digital I/O Register Description Port A Data Register - PORTA Port A Control Register - PACR Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Timer/Counter0 Timer/Counter Prescaler Register Description Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Register Description Watchdog Timer Control Register - WDTCR Hardware Modulator Register Description Modulation Control Register - MODCR Analog Comparator Register Description Analog Comparator Control and Status Register - ACSR Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Parallel Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 32M1-A Errata All revisions Datasheet Revision History Rev - 01/06G Rev - 01/06G Rev - 03/05F Table of Contents
The I/O space definition of the ATtiny28 is shown in Table 3.
Table 3.
ATtiny28 I/O Space
Address Hex Name Function
$3F SREG Status Register $1B PORTA Data Register, Port A $1A PACR Port A Control Register $19 PINA Input Pins, Port A $16 PINB Input Pins, Port B $12 PORTD Data Register, Port D $11 DDRD Data Direction Register, Port D $10 PIND Input Pins, Port D $08 ACSR Analog Comparator Control and Status Register $07 MCUCS MCU Control and Status Register $06 ICR Interrupt Control Register $05 IFR Interrupt Flag Register $04 TCCR0 Timer/Counter0 Control Register $03 TCNT0 Timer/Counter0 (8-bit) $02 MODCR Modulation Control Register $01 WDTCR Watchdog Timer Control Register $00 OSCCAL Oscillator Calibration Register Note: Reserved and unused locations are not shown in the table. All ATtiny28 I/O and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general-pur- pose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set section for more details. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. The I/O and peripherals control registers are explained in the following sections.
10 ATtiny28L/V
1062F–AVR–07/06 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA3..PA0) Port B (PB7..PB0) Port D (PD7..PD0) XTAL1 XTAL2 RESET Architectural Overview ALU - Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File Status Register Status Register - SREG System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock External RC Oscillator Register Description Oscillator Calibration Register - OSCCAL Memories I/O Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction Memory Access and Instruction Execution Timing Flash Program Memory Sleep Modes Idle Mode Power-down Mode System Control and Reset Reset Sources Power-on Reset External Reset Watchdog Reset Register Description MCU Control and Status Register - MCUCS Interrupts Reset and Interrupt Interrupt Handling Interrupt Response Time External Interrupt Low-level Input Interrupt Register Description Interrupt Control Register - ICR Interrupt Flag Register - IFR I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 Port A Schematics Port B Port B as General Digital Input Alternate Functions of Port B Port B Schematics Port D Port D as General Digital I/O Register Description Port A Data Register - PORTA Port A Control Register - PACR Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Timer/Counter0 Timer/Counter Prescaler Register Description Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Register Description Watchdog Timer Control Register - WDTCR Hardware Modulator Register Description Modulation Control Register - MODCR Analog Comparator Register Description Analog Comparator Control and Status Register - ACSR Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Parallel Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 32M1-A Errata All revisions Datasheet Revision History Rev - 01/06G Rev - 01/06G Rev - 03/05F Table of Contents
