Datasheet AT90CAN32, AT90CAN64, AT90CAN128 - Complete (Atmel) - 2
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with32K/64K/128K Bytes ofISP Flash and CAN Controlle |
| Pages / Page | 428 / 2 — Description. 1.1. Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128. … |
| File Format / Size | PDF / 5.3 Mb |
| Document Language | English |
Description. 1.1. Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128. Table 1-1. Device. Flash. EEPROM. RAM. 1.2. Part Description
Model Line for this Datasheet
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1. Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128
AT90CAN32, AT90CAN64 and AT90CAN128 are hardware and software compatible. They dif- fer only in memory sizes as shown in Table 1-1.
Table 1-1.
Memory Size Summary
Device Flash EEPROM RAM
AT90CAN32 32K Bytes 1K Byte 2K Bytes AT90CAN64 64K Bytes 2K Bytes 4K Bytes AT90CAN128 128K Bytes 4K Byte 4K Bytes
1.2 Part Description
The AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Pro- grammable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM, 2K/4K/4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN con- troller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differ- ential input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and five software selectable power sav- ing modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main- tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By
2 AT90CAN32/64/128
7679H–CAN–08/08 Document Outline 1. Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 1.2 Part Description 1.3 Disclaimer 1.4 Block Diagram 1.5 Pin Configurations 1.6 Pin Descriptions 2. About Code Examples 3. AVR CPU Core 3.1 Introduction 3.2 Architectural Overview 3.3 ALU - Arithmetic Logic Unit 3.4 Status Register 3.5 General Purpose Register File 3.6 Stack Pointer 3.7 Instruction Execution Timing 3.8 Reset and Interrupt Handling 4. Memories 4.1 In-System Reprogrammable Flash Program Memory 4.2 SRAM Data Memory 4.3 EEPROM Data Memory 4.4 I/O Memory 4.5 External Memory Interface 4.6 General Purpose I/O Registers 5. System Clock 5.1 Clock Systems and their Distribution 5.2 Clock Sources 5.3 Default Clock Source 5.4 Crystal Oscillator 5.5 Low-frequency Crystal Oscillator 5.6 Calibrated Internal RC Oscillator 5.7 External Clock 5.8 Clock Output Buffer 5.9 Timer/Counter2 Oscillator 5.10 System Clock Prescaler 6. Power Management and Sleep Modes 6.1 Idle Mode 6.2 ADC Noise Reduction Mode 6.3 Power-down Mode 6.4 Power-save Mode 6.5 Standby Mode 6.6 Minimizing Power Consumption 7. System Control and Reset 7.1 Reset 7.2 Internal Voltage Reference 7.3 Watchdog Timer 7.4 Timed Sequences for Changing the Configuration of the Watchdog Timer 8. Interrupts 8.1 Interrupt Vectors in AT90CAN32/64/128 8.2 Moving Interrupts Between Application and Boot Space 9. I/O-Ports 9.1 Introduction 9.2 Ports as General Digital I/O 9.3 Alternate Port Functions 9.4 Register Description for I/O-Ports 10. External Interrupts 10.1 External Interrupt Register Description 11. Timer/Counter3/1/0 Prescalers 11.1 Overview 11.2 Timer/Counter0/1/3 Prescalers Register Description 12. 8-bit Timer/Counter0 with PWM 12.1 Features 12.2 Overview 12.3 Timer/Counter Clock Sources 12.4 Counter Unit 12.5 Output Compare Unit 12.6 Compare Match Output Unit 12.7 Modes of Operation 12.8 Timer/Counter Timing Diagrams 12.9 8-bit Timer/Counter Register Description 13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 13.1 Features 13.2 Overview 13.3 Accessing 16-bit Registers 13.4 Timer/Counter Clock Sources 13.5 Counter Unit 13.6 Input Capture Unit 13.7 Output Compare Units 13.8 Compare Match Output Unit 13.9 Modes of Operation 13.10 Timer/Counter Timing Diagrams 13.11 16-bit Timer/Counter Register Description 14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 14.1 Features 14.2 Overview 14.3 Timer/Counter Clock Sources 14.4 Counter Unit 14.5 Output Compare Unit 14.6 Compare Match Output Unit 14.7 Modes of Operation 14.8 Timer/Counter Timing Diagrams 14.9 8-bit Timer/Counter Register Description 14.10 Asynchronous operation of the Timer/Counter2 14.11 Timer/Counter2 Prescaler 15. Output Compare Modulator - OCM 15.1 Overview 15.2 Description 16. Serial Peripheral Interface - SPI 16.1 Features 16.2 SS Pin Functionality 16.3 Data Modes 17. USART (USART0 and USART1) 17.1 Features 17.2 Overview 17.3 Dual USART 17.4 Clock Generation 17.5 Serial Frame 17.6 USART Initialization 17.7 Data Transmission - USART Transmitter 17.8 Data Reception - USART Receiver 17.9 Asynchronous Data Reception 17.10 Multi-processor Communication Mode 17.11 USART Register Description 17.12 Examples of Baud Rate Setting 18. Two-wire Serial Interface 18.1 Features 18.2 Two-wire Serial Interface Bus Definition 18.3 Data Transfer and Frame Format 18.4 Multi-master Bus Systems, Arbitration and Synchronization 18.5 Overview of the TWI Module 18.6 TWI Register Description 18.7 Using the TWI 18.8 Transmission Modes 18.9 Multi-master Systems and Arbitration 19. Controller Area Network - CAN 19.1 Features 19.2 CAN Protocol 19.3 CAN Controller 19.4 CAN Channel 19.5 Message Objects 19.6 CAN Timer 19.7 Error Management 19.8 Interrupts 19.9 CAN Register Description 19.10 General CAN Registers 19.11 MOb Registers 19.12 Examples of CAN Baud Rate Setting 20. Analog Comparator 20.1 Overview 20.2 Analog Comparator Register Description 20.3 Analog Comparator Multiplexed Input 21. Analog to Digital Converter - ADC 21.1 Features 21.2 Operation 21.3 Starting a Conversion 21.4 Prescaling and Conversion Timing 21.5 Changing Channel or Reference Selection 21.6 ADC Noise Canceler 21.7 ADC Conversion Result 21.8 ADC Register Description 22. JTAG Interface and On-chip Debug System 22.1 Features 22.2 Overview 22.3 Test Access Port - TAP 22.4 TAP Controller 22.5 Using the Boundary-scan Chain 22.6 Using the On-chip Debug System 22.7 On-chip Debug Specific JTAG Instructions 22.8 On-chip Debug Related Register in I/O Memory 22.9 Using the JTAG Programming Capabilities 22.10 Bibliography 23. Boundary-scan IEEE 1149.1 (JTAG) 23.1 Features 23.2 System Overview 23.3 Data Registers 23.4 Boundary-scan Specific JTAG Instructions 23.5 Boundary-scan Related Register in I/O Memory 23.6 Boundary-scan Chain 23.7 AT90CAN32/64/128 Boundary-scan Order 23.8 Boundary-scan Description Language Files 24. Boot Loader Support - Read-While-Write Self-Programming 24.1 Features 24.2 Application and Boot Loader Flash Sections 24.3 Read-While-Write and No Read-While-Write Flash Sections 24.4 Boot Loader Lock Bits 24.5 Entering the Boot Loader Program 24.6 Addressing the Flash During Self-Programming 24.7 Self-Programming the Flash 25. Memory Programming 25.1 Program and Data Memory Lock Bits 25.2 Fuse Bits 25.3 Signature Bytes 25.4 Calibration Byte 25.5 Parallel Programming Overview 25.6 Parallel Programming 25.7 SPI Serial Programming Overview 25.8 SPI Serial Programming 25.9 JTAG Programming Overview 26. Electrical Characteristics (1) 26.1 Absolute Maximum Ratings* 26.2 DC Characteristics 26.3 External Clock Drive Characteristics 26.4 Maximum Speed vs. VCC 26.5 Two-wire Serial Interface Characteristics 26.6 SPI Timing Characteristics 26.7 CAN Physical Layer Characteristics 26.8 ADC Characteristics 26.9 External Data Memory Characteristics 26.10 Parallel Programming Characteristics 27. Decoupling Capacitors 28. AT90CAN32/64/128 Typical Characteristics 28.1 Active Supply Current 28.2 Idle Supply Current 28.3 Power-down Supply Current 28.4 Power-save Supply Current 28.5 Standby Supply Current 28.6 Pin Pull-up 28.7 Pin Driver Strength 28.8 Pin Thresholds and Hysteresis 28.9 BOD Thresholds and Analog Comparator Offset 28.10 Internal Oscillator Speed 28.11 Current Consumption of Peripheral Units 28.12 Current Consumption in Reset and Reset Pulse Width 29. Register Summary 30. Instruction Set Summary 31. Ordering Information 32. Packaging Information 32.1 TQFP64 32.2 QFN64 33. Errata 33.1 Errata Summary 33.2 Errata Description 34. Datasheet Revision History for AT90CAN32/64/128 34.1 Changes from 7679G - 03/08 to 7679H - 08/08 34.2 Changes from 7679F - 11/07 to 7679G - 03/08 34.3 Changes from 7679E - 07/07 to 7679F - 11/07 34.4 Changes from 7679D - 02/07 to 7679E - 07/07 34.5 Changes from 7679C - 01/07 to 7679D - 02/07 34.6 Changes from 7679B - 11/06 to 7679C - 01/07 34.7 Changes from 7679A - 10/06 to 7679B - 11/06 34.8 Document Creation
1. Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128
AT90CAN32, AT90CAN64 and AT90CAN128 are hardware and software compatible. They dif- fer only in memory sizes as shown in Table 1-1.
Table 1-1.
Memory Size Summary
Device Flash EEPROM RAM
AT90CAN32 32K Bytes 1K Byte 2K Bytes AT90CAN64 64K Bytes 2K Bytes 4K Bytes AT90CAN128 128K Bytes 4K Byte 4K Bytes
1.2 Part Description
The AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Pro- grammable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM, 2K/4K/4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN con- troller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differ- ential input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and five software selectable power sav- ing modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main- tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By
2 AT90CAN32/64/128
7679H–CAN–08/08 Document Outline 1. Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 1.2 Part Description 1.3 Disclaimer 1.4 Block Diagram 1.5 Pin Configurations 1.6 Pin Descriptions 2. About Code Examples 3. AVR CPU Core 3.1 Introduction 3.2 Architectural Overview 3.3 ALU - Arithmetic Logic Unit 3.4 Status Register 3.5 General Purpose Register File 3.6 Stack Pointer 3.7 Instruction Execution Timing 3.8 Reset and Interrupt Handling 4. Memories 4.1 In-System Reprogrammable Flash Program Memory 4.2 SRAM Data Memory 4.3 EEPROM Data Memory 4.4 I/O Memory 4.5 External Memory Interface 4.6 General Purpose I/O Registers 5. System Clock 5.1 Clock Systems and their Distribution 5.2 Clock Sources 5.3 Default Clock Source 5.4 Crystal Oscillator 5.5 Low-frequency Crystal Oscillator 5.6 Calibrated Internal RC Oscillator 5.7 External Clock 5.8 Clock Output Buffer 5.9 Timer/Counter2 Oscillator 5.10 System Clock Prescaler 6. Power Management and Sleep Modes 6.1 Idle Mode 6.2 ADC Noise Reduction Mode 6.3 Power-down Mode 6.4 Power-save Mode 6.5 Standby Mode 6.6 Minimizing Power Consumption 7. System Control and Reset 7.1 Reset 7.2 Internal Voltage Reference 7.3 Watchdog Timer 7.4 Timed Sequences for Changing the Configuration of the Watchdog Timer 8. Interrupts 8.1 Interrupt Vectors in AT90CAN32/64/128 8.2 Moving Interrupts Between Application and Boot Space 9. I/O-Ports 9.1 Introduction 9.2 Ports as General Digital I/O 9.3 Alternate Port Functions 9.4 Register Description for I/O-Ports 10. External Interrupts 10.1 External Interrupt Register Description 11. Timer/Counter3/1/0 Prescalers 11.1 Overview 11.2 Timer/Counter0/1/3 Prescalers Register Description 12. 8-bit Timer/Counter0 with PWM 12.1 Features 12.2 Overview 12.3 Timer/Counter Clock Sources 12.4 Counter Unit 12.5 Output Compare Unit 12.6 Compare Match Output Unit 12.7 Modes of Operation 12.8 Timer/Counter Timing Diagrams 12.9 8-bit Timer/Counter Register Description 13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 13.1 Features 13.2 Overview 13.3 Accessing 16-bit Registers 13.4 Timer/Counter Clock Sources 13.5 Counter Unit 13.6 Input Capture Unit 13.7 Output Compare Units 13.8 Compare Match Output Unit 13.9 Modes of Operation 13.10 Timer/Counter Timing Diagrams 13.11 16-bit Timer/Counter Register Description 14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 14.1 Features 14.2 Overview 14.3 Timer/Counter Clock Sources 14.4 Counter Unit 14.5 Output Compare Unit 14.6 Compare Match Output Unit 14.7 Modes of Operation 14.8 Timer/Counter Timing Diagrams 14.9 8-bit Timer/Counter Register Description 14.10 Asynchronous operation of the Timer/Counter2 14.11 Timer/Counter2 Prescaler 15. Output Compare Modulator - OCM 15.1 Overview 15.2 Description 16. Serial Peripheral Interface - SPI 16.1 Features 16.2 SS Pin Functionality 16.3 Data Modes 17. USART (USART0 and USART1) 17.1 Features 17.2 Overview 17.3 Dual USART 17.4 Clock Generation 17.5 Serial Frame 17.6 USART Initialization 17.7 Data Transmission - USART Transmitter 17.8 Data Reception - USART Receiver 17.9 Asynchronous Data Reception 17.10 Multi-processor Communication Mode 17.11 USART Register Description 17.12 Examples of Baud Rate Setting 18. Two-wire Serial Interface 18.1 Features 18.2 Two-wire Serial Interface Bus Definition 18.3 Data Transfer and Frame Format 18.4 Multi-master Bus Systems, Arbitration and Synchronization 18.5 Overview of the TWI Module 18.6 TWI Register Description 18.7 Using the TWI 18.8 Transmission Modes 18.9 Multi-master Systems and Arbitration 19. Controller Area Network - CAN 19.1 Features 19.2 CAN Protocol 19.3 CAN Controller 19.4 CAN Channel 19.5 Message Objects 19.6 CAN Timer 19.7 Error Management 19.8 Interrupts 19.9 CAN Register Description 19.10 General CAN Registers 19.11 MOb Registers 19.12 Examples of CAN Baud Rate Setting 20. Analog Comparator 20.1 Overview 20.2 Analog Comparator Register Description 20.3 Analog Comparator Multiplexed Input 21. Analog to Digital Converter - ADC 21.1 Features 21.2 Operation 21.3 Starting a Conversion 21.4 Prescaling and Conversion Timing 21.5 Changing Channel or Reference Selection 21.6 ADC Noise Canceler 21.7 ADC Conversion Result 21.8 ADC Register Description 22. JTAG Interface and On-chip Debug System 22.1 Features 22.2 Overview 22.3 Test Access Port - TAP 22.4 TAP Controller 22.5 Using the Boundary-scan Chain 22.6 Using the On-chip Debug System 22.7 On-chip Debug Specific JTAG Instructions 22.8 On-chip Debug Related Register in I/O Memory 22.9 Using the JTAG Programming Capabilities 22.10 Bibliography 23. Boundary-scan IEEE 1149.1 (JTAG) 23.1 Features 23.2 System Overview 23.3 Data Registers 23.4 Boundary-scan Specific JTAG Instructions 23.5 Boundary-scan Related Register in I/O Memory 23.6 Boundary-scan Chain 23.7 AT90CAN32/64/128 Boundary-scan Order 23.8 Boundary-scan Description Language Files 24. Boot Loader Support - Read-While-Write Self-Programming 24.1 Features 24.2 Application and Boot Loader Flash Sections 24.3 Read-While-Write and No Read-While-Write Flash Sections 24.4 Boot Loader Lock Bits 24.5 Entering the Boot Loader Program 24.6 Addressing the Flash During Self-Programming 24.7 Self-Programming the Flash 25. Memory Programming 25.1 Program and Data Memory Lock Bits 25.2 Fuse Bits 25.3 Signature Bytes 25.4 Calibration Byte 25.5 Parallel Programming Overview 25.6 Parallel Programming 25.7 SPI Serial Programming Overview 25.8 SPI Serial Programming 25.9 JTAG Programming Overview 26. Electrical Characteristics (1) 26.1 Absolute Maximum Ratings* 26.2 DC Characteristics 26.3 External Clock Drive Characteristics 26.4 Maximum Speed vs. VCC 26.5 Two-wire Serial Interface Characteristics 26.6 SPI Timing Characteristics 26.7 CAN Physical Layer Characteristics 26.8 ADC Characteristics 26.9 External Data Memory Characteristics 26.10 Parallel Programming Characteristics 27. Decoupling Capacitors 28. AT90CAN32/64/128 Typical Characteristics 28.1 Active Supply Current 28.2 Idle Supply Current 28.3 Power-down Supply Current 28.4 Power-save Supply Current 28.5 Standby Supply Current 28.6 Pin Pull-up 28.7 Pin Driver Strength 28.8 Pin Thresholds and Hysteresis 28.9 BOD Thresholds and Analog Comparator Offset 28.10 Internal Oscillator Speed 28.11 Current Consumption of Peripheral Units 28.12 Current Consumption in Reset and Reset Pulse Width 29. Register Summary 30. Instruction Set Summary 31. Ordering Information 32. Packaging Information 32.1 TQFP64 32.2 QFN64 33. Errata 33.1 Errata Summary 33.2 Errata Description 34. Datasheet Revision History for AT90CAN32/64/128 34.1 Changes from 7679G - 03/08 to 7679H - 08/08 34.2 Changes from 7679F - 11/07 to 7679G - 03/08 34.3 Changes from 7679E - 07/07 to 7679F - 11/07 34.4 Changes from 7679D - 02/07 to 7679E - 07/07 34.5 Changes from 7679C - 01/07 to 7679D - 02/07 34.6 Changes from 7679B - 11/06 to 7679C - 01/07 34.7 Changes from 7679A - 10/06 to 7679B - 11/06 34.8 Document Creation
