Datasheet ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 (Analog Devices) - 10

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ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
I/O Input Currents IIA, IIB, IIC, IID −20 +0.01 +20 µA Logic High Input Threshold VIH 2.0 V Logic Low Input Threshold VIL 0.8 V Logic High Output Voltages VOAH, VOBH, VDD1 − 0.3, 5.0 V IOx = −20 µA, VIx = VIxH VOCH, VODH VISO − 0.3 VDD1 − 0.5, 4.8 V IOx = −4 mA, VIx = VIxH VISO − 0.5 Logic Low Output Voltages VOAL, VOBL, 0.0 0.1 V IOx = 20 µA, VIx = VIxL VOCL, VODL 0.0 0.4 V IOx = 4 mA, VIx = VIxL AC SPECIFICATIONS A Grade CL = 15 pF, CMOS signal levels Minimum Pulse Width PW 1000 ns Maximum Data Rate 1 Mbps Propagation Delay tPHL, tPLH 55 100 ns Pulse Width Distortion, |tPLH − tPHL| PWD 40 ns Propagation Delay Skew tPSK 50 ns Channel-to-Channel Matching tPSKCD/tPSKOD 50 ns C Grade CL = 15 pF, CMOS signal levels Minimum Pulse Width PW 40 ns Maximum Data Rate 25 Mbps Propagation Delay tPHL, tPLH 30 45 60 ns Pulse Width Distortion, |tPLH − tPHL| PWD 8 ns Change vs. Temperature 5 ps/°C Propagation Delay Skew tPSK 15 ns Channel-to-Channel Matching Codirectional Channels tPSKCD 8 ns Opposing Directional Channels tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity VCM = 1000 V, transient magnitude = 800 V At Logic High Output |CMH| 25 35 kV/µs VIx = VDD1 or VISO At Logic Low Output |CML| 25 35 kV/µs VIx = 0 V Refresh Rate fr 1.0 Mbps 1 The contributions of supply current values for all four channels are combined at identical data rates. 2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate. Rev. B | Page 10 of 36 Document Outline Features Applications General Description Functional Block Diagrams Table of Contents Revision History Specifications Electrical Characterstics—5 V Primary Input Supply/5 V Secondary Isolated Supply Electrical Characteristics—3.3 V Primary Input Supply/3.3 V Secondary Isolated Supply Electrical Characteristics—5 V Primary Input Supply/3.3 V Secondary Isolated Supply Electrical Characteristics—5 V Primary Input Supply/15 V Secondary Isolated Supply Package Characteristics Regulatory Approvals Insulation and Safety-Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics Recommended Operating Conditions Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Applications Information Application Schematics Transformer Design Transformer Turns Ratio Transformer ET Constant Transformer Primary Inductance and Resistance Transformer Isolation Voltage Switching Frequency Transient Response Component Selection Printed Circuit Board (PCB) Layout Thermal Analysis Propagation Delay-Related Parameters DC Correctness and Magnetic Field Immunity Power Consumption Power Considerations Soft Start Mode and Current-Limit Protection Data Channel Power Cycle Insulation Lifetime Outline Dimensions Ordering Guide Automotive Products