Datasheet ADuM5240, ADuM5241, ADuM5242 (Analog Devices) - 4

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ADuM5240/ADuM5241/ADuM5242 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions
AC SPECIFICATIONS Minimum Pulse Width5 PW 100 ns C = 15 pF, CMOS signal levels L Maximum Data Rate6 1 Mbps C = 15 pF, CMOS signal levels L Propagation Delay7 t , t 25 70 ns C = 15 pF, CMOS signal levels PHL PLH L Pulse Width Distortion, |t − t |8 PWD 3 ns C = 15 pF, CMOS signal levels PLH PHL L Propagation Delay Skew8 t 45 ns C = 15 pF, CMOS signal levels PSK L Channel-to-Channel Matching, t 3 ns C = 15 pF, CMOS signal levels PSKCD L Codirectional Channels9 Channel-to-Channel Matching, t 15 ns C = 15 pF, CMOS signal levels PSKCD L Opposing-Directional Channels9 Output Rise/Fall Time (10% to 90%) t /t 2.5 ns C = 15 pF, CMOS signal levels R F L Common-Mode Transient |CM | 25 35 kV/µs V = V , V , V = 1000 V, H Ix DD ISO CM Immunity at Logic High Output transient magnitude = 800 V Common-Mode Transient |CM | 25 35 kV/µs V = 0 V, V = 1000 V, L Ix CM Immunity at Logic Low Output transient magnitude = 800 V Refresh Frequency f 1.0 MHz r Switching Frequency f 300 MHz OSC 1 Peak noise occurs at frequency corresponding to the refresh frequency (see the PCB Layout section). 2 IDD (DISABLE) supply current values are specified with no load present on the digital outputs. 3 IISO (DISABLE) supply current values are specified with no load present on the digital outputs and power sourced by an external supply. 4 Enable/disable threshold is the VDD voltage at which the internal dc-to-dc converter is enabled/disabled. 5 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 6 The maximum data rate is the fastest data rate at which the specified pulse width distortion and VISO supply voltage is guaranteed. 7 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 8 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 9 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. Rev. B | Page 4 of 16 Document Outline Features General Description Functional Block Diagrams Table of Contents Revision History Specifications Electrical Characteristics Package Characteristics Regulatory Information Insulation and Safety-Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Recommended Operating Conditions Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Applications Information DC-to-DC Converter Propagation Delay-Related Parameters DC Correctness and Magnetic Field Immunity Thermal Analysis PCB Layout Increasing Available Power Insulation Lifetime Outline Dimensions Ordering Guide