HD44780UHD44780U Block Diagram OSC1 OSC2 CL1 CL2 M Reset circuit Timing ACL CPG generator Instruction 7 register (IR) D 8 Display COM1 to MPU Instruction data RAM 16-bit Common COM16 RS inter- decoder (DDRAM) shift signal R/W face 80 × 8 bits register driver E Address 7 SEG1 to counter 40-bit 40-bit Segment SEG40 8 7 shift latch signal DB4 to register circuit driver DB7 7 Input/ Data 8 8 DB0 to output register 40 DB3 buffer (DR) 8 8 LCD drive voltage Busy selector flag Character Character Cursor generator generator and RAM ROM blink (CGRAM) (CGROM) controller 64 bytes 9,920 bits GND 5 5 Parallel/serial converter and attribute circuit VCC V1 V2 V3 V4 V5 3 Document Outline Description Features Ordering Information HD44780U Block Diagram HD44780U Pin Arrangement (FP-80B) HD44780U Pin Arrangement (TFP-80F) HD44780U Pad Arrangement HD44780U Pad Location Coordinates Pin Functions Function Description Interfacing to the MPU Reset Function Instructions Instruction Description Interfacing the HD44780U Power Supply for Liquid Crystal Display Drive Relationship between Oscillation Frequency and Liquid Crystal Display Frame Frequency Instruction and Display Correspondence Initializing by Instruction Absolute Maximum Ratings DC Characteristics AC Characteristics Bus Timing Characteristics Interface Timing Characteristics with External Driver Power Supply Conditions Using Internal Reset Circuit DC Characteristics AC Characteristics Bus Timing Characteristics Interface Timing Characteristics with External Driver Power Supply Conditions Using Internal Reset Circuit Electrical Characteristics Notes Load Circuits Timing Characteristics