Datasheet PCF8574, PCF8574A (NXP) - 7

NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt
There is only one register to control four possibilities of the port pin: Input HIGH, input LOW, output HIGH, or output LOW.
Input HIGH:
The master needs to write 1 to the register to set the port as an input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin up to VDD or drives logic 1, then the master will read the value of 1.
Input LOW:
The master needs to write 1 to the register to set the port to input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin down to VSS or drives logic 0, which sinks the weak 100 A current source, then the master will read the value of 0.
Output HIGH:
The master writes 1 to the register. There is an additional ‘accelerator’ or strong pull-up current when the master sets the port HIGH. The additional strong pull-up is only active during the HIGH time of the acknowledge clock cycle. This accelerator current helps the port’s 100 A current source make a faster rising edge into a heavily loaded output, but only at the start of the acknowledge clock cycle to avoid bus contention if an external signal is pulling the port LOW to VSS/driving the port with logic 0 at the same time. After the half clock cycle there is only the 100 A current source to hold the port HIGH.
Output LOW:
The master writes 0 to the register. There is a strong current sink transistor that holds the port pin LOW. A large current may flow into the port, which could potentially damage the part if the master writes a 0 to the register and an external source is pulling the port HIGH at the same time. VDD input HIGH weak 100 µA current source pull-up with output HIGH (inactive when resistor to VDD or output LOW) external drive HIGH accelerator pull-up P port P7 - P0 pull-down with output LOW resistor to VSS or external drive LOW input LOW VSS 002aah683
Fig 7. Simple quasi-bidirectional I/O
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 7 of 33
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 4.1 Ordering options 5. Block diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 7.1 Device address 7.1.1 Address maps 8. I/O programming 8.1 Quasi-bidirectional I/Os 8.2 Writing to the port (Output mode) 8.3 Reading from a port (Input mode) 8.4 Power-on reset 8.5 Interrupt output (INT) 9. Characteristics of the I2C-bus 9.1 Bit transfer 9.1.1 START and STOP conditions 9.2 System configuration 9.3 Acknowledge 10. Application design-in information 10.1 Bidirectional I/O expander applications 10.2 How to read and write to I/O expander (example) 10.3 High current-drive load applications 10.4 Migration path 11. Limiting values 12. Thermal characteristics 13. Static characteristics 14. Dynamic characteristics 15. Package outline 16. Handling information 17. Soldering of SMD packages 17.1 Introduction to soldering 17.2 Wave and reflow soldering 17.3 Wave soldering 17.4 Reflow soldering 18. Soldering of through-hole mount packages 18.1 Introduction to soldering through-hole mount packages 18.2 Soldering by dipping or by solder wave 18.3 Manual soldering 18.4 Package related soldering information 19. Soldering: PCB footprints 20. Abbreviations 21. Revision history 22. Legal information 22.1 Data sheet status 22.2 Definitions 22.3 Disclaimers 22.4 Trademarks 23. Contact information 24. Contents