Datasheet LTM4639 (Analog Devices) - 7

LTM4639
PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY OT_TEST (B9)
: Used for Test Purposes. Float this pin, or
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
tie to VIN to disable overtemperature protection.
LAYOUT CAREFULLY. f V SET (B12):
A resistor can be applied from this pin to
IN (A1-A6, B1-B6, C1-C6):
Power Input Pins. Apply ground to set the operating frequency, or a DC voltage input voltage between these and GND pins. Recommend can be applied to set the frequency. See the Applications placing input decoupling capacitance directly between Information section. VIN and GND pins.
TRACK/SS (A9):
Output Voltage Tracking Pin and Soft-
VOUT (J1-J10, K1-K11, L1-L11, M1-M11):
Power Output Start Inputs. The pin has a 1.2µA pull-up current source. A Pins. Apply output load between these and GND pins. capacitor from this pin to ground will set a soft-start ramp Recommend placing output decoupling capacitance rate. In tracking, the regulator output can be tracked to a between these pins and GND pins. Review Table 5. Output different voltage. See the Applications Information section. range 0.6V to 5.5V.
V GND (C7, C9, D1-D6, D8, E1-E5, E7, E9, F1-F5, F7-F9, FB (F12):
The Negative Input of the Error Amplifier. Internally, this pin is connected to V
G1-G9, H1-H9):
Power Ground Pins for Both Input and OUT_LCL with a 60.4k precision resistor. Different output voltages can Output. be programmed with an additional resistor between VFB
PGOOD (F11, G12):
Output Voltage Power Good Indicator. and ground pins. In PolyPhase® operation, tying the Open-drain logic output is pulled to ground when the VFB pins together allows for parallel operation. See the output voltage exceeds a ±10% regulation window. Both Applications Information section. pins are tied together internally.
COMPA (A11):
Current Control Threshold and Error
SGND (G11, H11, H12):
Signal Ground Pin. Return Amplifier Compensation Point. The current comparator ground path for all analog and low power circuitry. Tie a threshold increases with this control voltage. Tie all single connection to the output capacitor GND. See layout COMP pins together for parallel operation. This pin can guidelines in Figure 21. be compensated externally for optimized loop response
TEMP+ (F6):
Temperature Monitor. See Applications In- or connected to the COMPB pin. See the Applications formation section. Information section.
TEMP– (E6):
Kelvin Return of the Internal Temperature
COMPB (A12):
Default Compensation Network Monitor. Corresponding to Table 5. Tie this pin to COMPA to use default compensation. See the Applications Information
MODE_PLLIN (A8):
Forced Continuous Mode, Burst section. Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin.
RUN (A10):
Run Control Pin. A voltage above 1.4V will turn Connect this pin to INTV on the module. A 5.1V Zener diode to ground is internal to CC to enable pulse-skipping mode. Connect to ground to enable forced continuous mode. the module for limiting the voltage on the RUN pin to 5V Floating this pin will enable Burst Mode operation. A clock on and allowing the use of a pull-up resistor to VIN for enabling this pin will enable synchronization with forced continuous the device. Limit current into the RUN pin to ≤ 2mA. operation. See the Applications Information section.
INTVCC (A7, D9):
Internal 5V LDO for Driving the Control
C
Circuitry and the Power MOSFET Drivers. Both pins are
PWR (B7):
Control Bias Input. Required to operate the LTM4639 regulator below 4.5V input. For V internally connected. The 5V LDO has a 100mA current IN ≥4.5V up to 7V connect C limit. INTVCC is controlled and enabled when RUN is PWR to VIN. To maintain soft-start function, sequence V activated high. See Applications Section. This pin is an IN before CPWR, then enable the RUN pin. If the RUN pin has a pull-up resistor to V output, do not drive this pin. IN, then sequence CPWR after VIN. 4639f For more information www.linear.com/LTM4639 7