Datasheet LTM4641 (Analog Devices) - 10

LTM4641
pin FuncTions SGND (A1-A3; B1-B3; C1-C4; K1, K3; L3; M1-M3):
Signal may be deasserted when TEMP subsequently exceeds Ground Pins. This is the return ground path for all analog 514mV (nominally corresponding to a cool-off hysteresis control and low power circuitry. SGND is tied to GND in- of ~10°C), depending on the OTBH setting. (See OTBH and ternal to the µModule regulator in a manner that promotes the Applications Information section.) the best internal signal integrity—therefore, SGND should To disable the µModule regulator’s overtemperature not be connected to GND in the user’s PCB layout. See shutdown feature, connect the TEMP and 1V the Layout Checklist/Example section of the Applications REF pins. The thermal shutdown inception threshold can also be modi- Information section for more information pertaining to fied, see the Applications Information section. SGND and layout. All SGND pins are electrically connected to each other, internally.
IOVRETRY (A6):
Nonlatching Input Overvoltage Threshold Programming Pin. The LTM4641 pulls HYST low to inhibit
HYST (A4):
Input Undervoltage Hysteresis Programming regulation of its output voltage when IOVRETRY exceeds Pin. Normally used as an output, but can be used as an 0.5V. The LTM4641 can resume switching action when input. If the LTM4641’s inherent, default undervoltage IOVRETRY is below 0.5V. If no nonlatching input over- lockout (UVLO) settings are satisfactory, 4.5VIN(RISING, voltage shutdown behavior is desired, connect this pin to MAX) and 4VIN(FALLING, MAX), HYST can be left electrically SGND. Do not leave this pin open circuit. open circuit. See the Applications Information section to customize the LTM4641’s UVLO thresholds.
GND (A7-A12; B6-B8, B11-B12; C7-C8; D6-D8; E1-E8; F1-F12; G1-G12; H3-H9, H11-H12; J5-J12; K5-K6, K11-
HYST is a logic-high output with moderate pull-up strength
K12; L4-L6; M4-M6):
Power ground pins for input and that commands LTM4641’s internal control IC to regulate output returns. See the Layout Checklist/Example section the module’s output voltage when conditions on the RUN, of the Applications Information section. All GND pins are UVLO, OVLO, IOVRETRY, TEMP, CROWBAR, INTVCC electrically connected to each other, internally. and DRVCC pins permit it (any recent latchoff events notwithstanding, otherwise OTBH and LATCH can also
UVLO (B4):
Input Undervoltage Lockout Programming play a role). When a fault condition is detected, internal Pin. The LTM4641 pulls HYST low to inhibit regulation circuitry (MHYST; see Figure 1) drives HYST logic low and of its output voltage whenever UVLO is less than 0.5V. the LTM4641’s output is turned off. HYST can be used as The LTM4641 can resume switching action when UVLO a fault-indicator. See the Applications Information section. exceeds 0.5V. Do not leave this pin open circuit. HYST is pulled low when the RUN pin is pulled low, via If the LTM4641’s default UVLO settings are used, an internal Schottky diode. HYST can be driven low by 4.5VIN(RISING, MAX) and 4VIN(FALLING, MAX), then the UVLO external open-collector/open-drain circuitry directly—as pin should be electrically connected to 1VREF or INTVCC. an alternate to the RUN pin interface. However, external Otherwise, see HYST and the Applications Information circuitry should never drive HYST high, since doing so section for using a resistor-divider network to implement (indiscriminately) could cause thermal overstress to personalized UVLO rising and UVLO falling settings. MHYST, when MHYST is on.
OVLO (B5):
Input Overvoltage Latchoff Programming Pin.
TEMP (A5):
Power Stage Temperature Indicator and LTM4641 pulls HYST low to inhibit regulation of its output Overtemperature Detection Pin. When left electrically open voltage when OVLO exceeds 0.5V. If OVLO subsequently circuit, TEMP’s voltage varies according to an internal NTC falls below 0.5V, the module’s output remains latched (negative temperature coefficient) thermistor, residing in off; the LTM4641 cannot resume regulation of the output close proximity to LTM4641’s power stage. When TEMP voltage until either the LATCH pin is toggled high or VINL falls below 438mV (corresponding to a thermistor and is power cycled. If input overvoltage latchoff behavior is power stage temperature of ~145°C), the LTM4641 pulls not desired, electrically short this pin to SGND. Do not HYST low to inhibit regulation of its output voltage. HYST leave this pin open circuit. 4641fe 10 For more information www.linear.com/LTM4641 Document Outline Features Applications Typical Application Description Table of Contents Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Operation Applications Information—Power Supply Features Applications Information—Input Protection Features Applications Information—Load Protection Features Applications Information—EMI Performance Applications Information—Multimodule Parallel Operation Applications Information—Thermal Considerations and Output Current Derating Applications Information—Output Capacitance Table Applications Information—Safety and Layout Guidance Typical Applications Appendices Package Description Package Photo Package Description Revision History Typical Application Related Parts