Datasheet LTM4619 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual, 26VIN, 4A DC/DC µModule Regulator |
| Pages / Page | 26 / 10 — applicaTions inForMaTion. Mode Selections and Phase-Locked Loop. … |
| File Format / Size | PDF / 570 Kb |
| Document Language | English |
applicaTions inForMaTion. Mode Selections and Phase-Locked Loop. Frequency Selection. Frequency Synchronization
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LTM4619
applicaTions inForMaTion Mode Selections and Phase-Locked Loop Frequency Selection
The LTM4619 can be enabled to enter high efficiency The switching frequency of the LTM4619’s controllers Burst Mode operation, constant-frequency pulse-skipping can be selected using the FREQ/PLLFLTR pin. If the mode, or forced continuous conduction mode. To select MODE/PLLIN pin is not being driven by an external clock the forced continuous operation, tie the MODE/PLLIN pin source, the FREQ/PLLFLTR pin can be set from 0V to 2.4V to to a DC voltage below 0.8V. To select pulse-skipping mode program the control er’s operating frequency from 250kHz of operation, tie the MODE/PLLIN pin to INTVCC. To select to 780kHz using a voltage divider to INTVCC (see Figure Burst Mode operation, float the MODE/PLLIN pin. 20). The typical frequency is 780kHz. If the output is too low or the minimum on-time is reached, the frequency
Frequency Synchronization
needs to decrease to enlarge the turn-on time. Otherwise, A phase-lock loop is available on the LTM4619 to syn- a significant amount of cycle skipping can occur with cor- chronize the internal clock to an external clock source respondingly larger current and voltage ripple. connected on the MODE/PLLIN pin. The clock high level needs to be higher than 1.6V and the clock low level needs 900 to be lower than 1V. The frequency programming voltage 800 and or the programming voltage divider must be removed 700 from the FREQ/PLLFLTR pin when synchronizing to an 600 external clock. The FREQ/PLLFLTR pin has the required 500 onboard PLL filter components for clock synchronization. 400 The LTM4619 will default to forced continuous mode while 300 being clock synchronized. Channel 1 is synchronized to 200 the rising edge on the external clock, and channel 2 is 180 SWITCHING FREQUENCY (kHz) 100 degrees out-of-phase with the external clock. 0 0 0.5 1 1.5 2 2.5 FREQ/PLLFLTR PIN VOLTAGE (V) 4619 F02
Figure 2. Switching Frequency vs FREQ/PLLFLTR Pin Voltage
4619fc 10 For more information www.linear.com/LTM4619 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photograph Related Parts Design Resources
applicaTions inForMaTion Mode Selections and Phase-Locked Loop Frequency Selection
The LTM4619 can be enabled to enter high efficiency The switching frequency of the LTM4619’s controllers Burst Mode operation, constant-frequency pulse-skipping can be selected using the FREQ/PLLFLTR pin. If the mode, or forced continuous conduction mode. To select MODE/PLLIN pin is not being driven by an external clock the forced continuous operation, tie the MODE/PLLIN pin source, the FREQ/PLLFLTR pin can be set from 0V to 2.4V to to a DC voltage below 0.8V. To select pulse-skipping mode program the control er’s operating frequency from 250kHz of operation, tie the MODE/PLLIN pin to INTVCC. To select to 780kHz using a voltage divider to INTVCC (see Figure Burst Mode operation, float the MODE/PLLIN pin. 20). The typical frequency is 780kHz. If the output is too low or the minimum on-time is reached, the frequency
Frequency Synchronization
needs to decrease to enlarge the turn-on time. Otherwise, A phase-lock loop is available on the LTM4619 to syn- a significant amount of cycle skipping can occur with cor- chronize the internal clock to an external clock source respondingly larger current and voltage ripple. connected on the MODE/PLLIN pin. The clock high level needs to be higher than 1.6V and the clock low level needs 900 to be lower than 1V. The frequency programming voltage 800 and or the programming voltage divider must be removed 700 from the FREQ/PLLFLTR pin when synchronizing to an 600 external clock. The FREQ/PLLFLTR pin has the required 500 onboard PLL filter components for clock synchronization. 400 The LTM4619 will default to forced continuous mode while 300 being clock synchronized. Channel 1 is synchronized to 200 the rising edge on the external clock, and channel 2 is 180 SWITCHING FREQUENCY (kHz) 100 degrees out-of-phase with the external clock. 0 0 0.5 1 1.5 2 2.5 FREQ/PLLFLTR PIN VOLTAGE (V) 4619 F02
Figure 2. Switching Frequency vs FREQ/PLLFLTR Pin Voltage
4619fc 10 For more information www.linear.com/LTM4619 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photograph Related Parts Design Resources
