Datasheet LTC4360-1, LTC4360-2 (Analog Devices) - 7

link to page 7 LTC4360-1/LTC4360-2
APPLICATIONS INFORMATION
The GATE ramp rate is limited to 3V/ms. VOUT follows at resistor from PWRGD to the I/O rail with a resistance a similar rate which results in an inrush current into the low enough to override the internal 500k pull-up to OUT. load capacitor COUT of: Figure 2 details PWRGD behavior for a LTC4360-1 with 1k pull-up to 5V at PWRGD. dV I GATE INRUSH = COUT • = COUT • 3 [mA/µF] dt START-UP RESTART RESTART FROM UVLO OV FROM OV ON FROM ON The servo loop is compensated by the parasitic capaci- tance of the external MOSFET. No further compensation VIN(OV) VIN(OV)–∆VOV components are normally required. In the case where the VIN(UVL) parasitic capacitance is less than 100pF, a 100pF com- IN pensation capacitor between GATE and ground may be required. OUT An even slower GATE ramp and lower inrush current VGATE(TH) VGATE(TH) VGATE(TH) VGATE(TH) can be achieved by connecting an external capacitor, CG, GATE from GATE to ground. The voltage at GATE then ramps up with a slope equal to 10µA/CG [V/s]. Choose CG using the formula: ON PWRGD 10µA CG = • COUT IINRUSH 130ms 65ms 130ms 65ms 130ms 65ms
Overvoltage Figure 2. PWRGD Behavior
When power is first applied, VIN must remain below 5.7V (VIN(OV) – ∆VOV) for more than 130ms before GATE is ramped up to turn on the MOSFET. If V
ON Input (LTC4360-1)
IN then rises above 5.8V (VIN(OV)), the overvoltage comparator activates the ON is a CMOS compatible, active low enable input. It 30mA fast pull-down on GATE within 1µs. After an over- has a default 5µA pull-down to ground. Connect this voltage condition, the MOSFET is held off until VIN once pin to ground or leave open to enable normal device again remains below 5.7V for 130ms. operation. If it is driven high while the external MOSFET is turned on, GATE is pulled low with a weak pull-down
PWRGD Output
current (40µA) to turn off the external MOSFET gradu- PWRGD is an active low output with a MOSFET pull- ally, minimizing input voltage transients. The LTC4360-1 down to ground and a 500k resistive pull-up to OUT. The then goes into a low current sleep mode, drawing only PWRGD pin pull-down releases during the low current 1.5µA at IN. When ON goes back low, the part restarts sleep mode (invoked by ON high), UVLO or overvoltage with a 130ms delay cycle. and the subsequent 130ms start-up delay. After the start- up delay, GATE starts its slow ramp-up and control of
GATEP Control (LTC4360-2)
the PWRGD pull-down passes on to the GATE high com- GATEP has a 2M resistive pull-down to ground and a 5.8V parator. VGATE > VGATE(TH) for more than 65ms asserts Zener clamp in series with a 200k resistor to IN. It con- the PWRGD pull-down and VGATE < VGATE(TH) releases trols the gate of an optional external P-channel MOSFET the pull-down. The PWRGD pull-down is capable of sink- to provide negative voltage protection. The 2M resistive ing up to 3mA of current allowing it to drive an optional pull-down turns on the MOSFET once VIN – VGATEP is LED. To interface PWRGD to another I/O rail, connect a more than the MOSFET gate threshold voltage. The IN to Rev B For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts