Datasheet LT3761, LT3761-1 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 60VIN LED Controller with Internal PWM Generator |
| Pages / Page | 32 / 8 — pin FuncTions. PWMOUT (Pin 1):. CTRL (Pin 6):. FB (Pin 2):. REF (Pin 7):. … |
| File Format / Size | PDF / 593 Kb |
| Document Language | English |
pin FuncTions. PWMOUT (Pin 1):. CTRL (Pin 6):. FB (Pin 2):. REF (Pin 7):. PWM (Pin 8):. ISN (Pin 3):. ISP (Pin 4):. VC (Pin 5):
Model Line for this Datasheet
Text Version of Document
LT3761/LT3761-1
pin FuncTions PWMOUT (Pin 1):
Buffered Version of PWM Signal for demand current state variable for the next PWM high Driving LED Load Disconnect NMOS or Level Shift. This transition. Connect a capacitor between this pin and GND; pin also serves in a protection function for the FB over- a resistor in series with the capacitor is recommended for voltage condition—will toggle if the FB input is greater fast transient response. than the FB regulation voltage (VFB) plus 60mV (typical).
CTRL (Pin 6):
Current Sense Threshold Adjustment Pin. The PWMOUT pin is driven from INTVCC. Use of a FET Constant current regulation point V with gate cut-off voltage higher than 1V is recommended. ISP-ISN is one-fourth VCTRL plus an offset for 0V ≤ CTRL ≤ 1V. For CTRL >
FB (Pin 2):
Voltage Loop Feedback Pin. FB is intended for 1.2V the VISP-ISN current regulation point is constant at constant-voltage regulation or for LED protection and open the full-scale value of 250mV. For 1V ≤ CTRL ≤ 1.2V, the LED detection. The internal transconductance amplifier with dependence of VISP-ISN upon CTRL voltage transitions output VC will regulate FB to 1.25V (nominal) through the from a linear function to a constant value, reaching 98% of DC/DC converter. If the FB input exceeds the regulation full-scale value by CTRL = 1.1V. Do not leave this pin open. voltage, VFB, minus 50mV and the voltage between ISP
V
and ISN has dropped below the C/10 threshold of 25mV
REF (Pin 7):
Voltage Reference Output Pin, Typically 2V. This pin drives a resistor divider for the CTRL pin, either (typical), the OPENLED pull-down is asserted. This action for analog dimming or for temperature limit/compensation may signal an open LED fault. If FB is driven above the FB of LED load. It can be bypassed with 10nF or greater, or overvoltage threshold, the PWMOUT and GATE pins will be less than 50pF. Can supply up to 185µA (typical). driven low to protect the LEDs from an overcurrent event. Do not leave the FB pin open. If not used, connect to GND.
PWM (Pin 8):
A signal low turns off switcher, idles the
ISN (Pin 3):
Connection Point for the Negative Terminal oscillator and disconnects the VC pin from all internal of the Current Feedback Resistor. The constant output loads. PWMOUT pin follows the PWM pin, except in fault current regulation can be programmed by I conditions. The PWM pin can be driven with a digital LED = 250mV/ R signal to cause pulse width modulation (PWM) dimming LED when CTRL > 1.2V or ILED = (CTRL – 100mV)/(4 • R of an LED load. The digital signal should be capable of LED). If ISN is greater than INTVCC, input bias current is typically 20μA flowing into the pin. Below INTV sourcing or sinking 200μA at the high and low thresholds. CC, ISN bias current decreases until it flows out of the pin. During start-up when DIM/SS is below 1V, the first rising edge of PWM enables switching which continues until
ISP (Pin 4):
Connection Point for the Positive Terminal of VISP-ISN ≥ 25mV or SS ≥ 1V. Connecting a capacitor from the Current Feedback Resistor. Input bias current depends PWM pin to GND invokes a self-driving oscillator where upon CTRL pin voltage. When it is greater than INTVCC internal pull-up and pull-down currents set a duty ratio it flows into the pin. Below INTVCC, ISP bias current for the PWMOUT pin for dimming LEDs. The magnitude decreases until it flows out of the pin. If the difference of the pull-up/down currents is set by the current in the between ISP and ISN exceeds 600mV (typical), then an DIM/SS pin. The capacitor on PWM sets the frequency of overcurrent event is detected. In response to this event, the dimming signal. For hiccup mode response to output the GATE and PWMOUT pins are driven low to protect the short-circuit faults, connect this pin as shown in the ap- switching regulator, a 1.5mA pull-down on PWM and a plication titled Boost LED Driver with Output Short-Circuit 9mA pull-down on the DIM/SS pin are activated for 4µs. Protection. If not used, connect the PWM pin to INTVCC.
VC (Pin 5):
Transconductance Error Amplifier Output Pin
OPENLED (Pin 9, LT3761 Only):
An open-drain pull-down Used to Stabilize the Switching Regulator Control Loop on this pin asserts if the FB input is greater than the FB with an RC Network. The VC pin is high impedance when regulation voltage (VFB) minus 50mV (typical) AND the PWM is low. This feature allows the VC pin to store the 37611fb 8 For more information www.linear.com/LT3761 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions PWMOUT (Pin 1):
Buffered Version of PWM Signal for demand current state variable for the next PWM high Driving LED Load Disconnect NMOS or Level Shift. This transition. Connect a capacitor between this pin and GND; pin also serves in a protection function for the FB over- a resistor in series with the capacitor is recommended for voltage condition—will toggle if the FB input is greater fast transient response. than the FB regulation voltage (VFB) plus 60mV (typical).
CTRL (Pin 6):
Current Sense Threshold Adjustment Pin. The PWMOUT pin is driven from INTVCC. Use of a FET Constant current regulation point V with gate cut-off voltage higher than 1V is recommended. ISP-ISN is one-fourth VCTRL plus an offset for 0V ≤ CTRL ≤ 1V. For CTRL >
FB (Pin 2):
Voltage Loop Feedback Pin. FB is intended for 1.2V the VISP-ISN current regulation point is constant at constant-voltage regulation or for LED protection and open the full-scale value of 250mV. For 1V ≤ CTRL ≤ 1.2V, the LED detection. The internal transconductance amplifier with dependence of VISP-ISN upon CTRL voltage transitions output VC will regulate FB to 1.25V (nominal) through the from a linear function to a constant value, reaching 98% of DC/DC converter. If the FB input exceeds the regulation full-scale value by CTRL = 1.1V. Do not leave this pin open. voltage, VFB, minus 50mV and the voltage between ISP
V
and ISN has dropped below the C/10 threshold of 25mV
REF (Pin 7):
Voltage Reference Output Pin, Typically 2V. This pin drives a resistor divider for the CTRL pin, either (typical), the OPENLED pull-down is asserted. This action for analog dimming or for temperature limit/compensation may signal an open LED fault. If FB is driven above the FB of LED load. It can be bypassed with 10nF or greater, or overvoltage threshold, the PWMOUT and GATE pins will be less than 50pF. Can supply up to 185µA (typical). driven low to protect the LEDs from an overcurrent event. Do not leave the FB pin open. If not used, connect to GND.
PWM (Pin 8):
A signal low turns off switcher, idles the
ISN (Pin 3):
Connection Point for the Negative Terminal oscillator and disconnects the VC pin from all internal of the Current Feedback Resistor. The constant output loads. PWMOUT pin follows the PWM pin, except in fault current regulation can be programmed by I conditions. The PWM pin can be driven with a digital LED = 250mV/ R signal to cause pulse width modulation (PWM) dimming LED when CTRL > 1.2V or ILED = (CTRL – 100mV)/(4 • R of an LED load. The digital signal should be capable of LED). If ISN is greater than INTVCC, input bias current is typically 20μA flowing into the pin. Below INTV sourcing or sinking 200μA at the high and low thresholds. CC, ISN bias current decreases until it flows out of the pin. During start-up when DIM/SS is below 1V, the first rising edge of PWM enables switching which continues until
ISP (Pin 4):
Connection Point for the Positive Terminal of VISP-ISN ≥ 25mV or SS ≥ 1V. Connecting a capacitor from the Current Feedback Resistor. Input bias current depends PWM pin to GND invokes a self-driving oscillator where upon CTRL pin voltage. When it is greater than INTVCC internal pull-up and pull-down currents set a duty ratio it flows into the pin. Below INTVCC, ISP bias current for the PWMOUT pin for dimming LEDs. The magnitude decreases until it flows out of the pin. If the difference of the pull-up/down currents is set by the current in the between ISP and ISN exceeds 600mV (typical), then an DIM/SS pin. The capacitor on PWM sets the frequency of overcurrent event is detected. In response to this event, the dimming signal. For hiccup mode response to output the GATE and PWMOUT pins are driven low to protect the short-circuit faults, connect this pin as shown in the ap- switching regulator, a 1.5mA pull-down on PWM and a plication titled Boost LED Driver with Output Short-Circuit 9mA pull-down on the DIM/SS pin are activated for 4µs. Protection. If not used, connect the PWM pin to INTVCC.
VC (Pin 5):
Transconductance Error Amplifier Output Pin
OPENLED (Pin 9, LT3761 Only):
An open-drain pull-down Used to Stabilize the Switching Regulator Control Loop on this pin asserts if the FB input is greater than the FB with an RC Network. The VC pin is high impedance when regulation voltage (VFB) minus 50mV (typical) AND the PWM is low. This feature allows the VC pin to store the 37611fb 8 For more information www.linear.com/LT3761 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
