Datasheet LTC4110 (Analog Devices) - 6

LTC4110
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. Unless otherwise specifi ed, VDCIN = VDCOUT = VDCDIV = 12V, VBAT = 8.4V, GND = SGND = CLP = CLN = SHDN = 0V and RVREF = 49.9k. All currents into device pins are positive and all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise specifi ed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREMH THB Pin Battery Removal Threshold VTHB Decreasing; Lead Acid Only 25 mV Hysteresis Voltage
Logic and Status Output Levels
VILS SCL/SDA Input Pins Low Voltage l 0.8 V VIHS SCL/SDA Input Pins High Voltage l 2.1 V VOLS SDA Output Pin Low Voltage IPULL-UP = 350μA l 0.4 V VOLG ACPb, GPIO1,2,3 Output Pins Low Voltage IACPb, IGPIO1, IGPIO2, IGPIO3 = 10mA 1 V IOHG ACPb, GPIO1,2,3 Output Pins Open Leakage Current Outputs Open, VACPb, VGPIO1,2,3 = 5V –2 2 μA VILG GPIO Input Low Voltage l 1 V VIHG GPIO Input High Voltage l 1.5 V VILSD SHDN Input Pin Low Voltage 0.5 V VIHSD SHDN Input Pin High Voltage 2.4 V IISD SHDN Input Pin Pull-Up Current VSHDN = 2.4V –3.5 –2 –1 μA TLR Logic Reset Duration After Power-Up VDCIN Transition From 0V to 5V in <1ms; 1 s From Zero VBAT = 0
SMBus Timing (Note 9)
tHIGH SCL Serial Clock High Period IPULL-UP = 350μA, CLOAD = 250pF, l 4 μs RPU = 9.31k tLOW SCL Serial Clock Low Period IPULL-UP = 350μA, CLOAD = 250pF, l 4.7 μs RPU = 9.31k tTO Timeout Period l 25 ms tF SDA/SCL Fall Time CLOAD = 250pF, RPU = 9.31k l 300 ns tSU-STA Start Condition Set-Up Time l 4.7 μs tHD-STA Start Condition Hold Time l 4 μs tHD-DAT SDA to SCL Falling-Edge Hold Time, l 300 ns Slave Clocking in Data
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
The LTC4110 is idle with no application load. It is not charging may cause permanent damage to the device. Exposure to any Absolute or calibrating the battery and is not in backup or shutdown mode. The Maximum Rating condition for extended periods may affect device internal clock is running and the SMBus is functional. reliability and lifetime. Specifi c functionality or parametric performance
Note 5:
Combined current of CSP, CSN and BAT pins set to VBAT with no of the device beyond the limits expressly given in the Electrical application load. Characteristics table is not implied by these maximum ratings.
Note 6:
CTH is defi ned as the sum of capacitance on THA, THB
Note 2:
The LTC4110E is guaranteed to meet performance specifi cations SafetySignal. from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
Note 7:
Does not include tolerance of current sense or current temperature range are assured by design, characterization and correlation programming resistors. with statistical process controls.
Note 8:
Given as a per cell voltage referred to the BAT pin (VBAT/number of
Note 3:
This IC includes overtemperature protection that is intended series cells). to protect the device during momentary overload conditions.
Note 9:
Refer to System Management Bus Specifi cation, Revision 1.1, Overtemperature protection will become active at a junction temperature section 2.1 for Timing Diagrams and section 8.1, for t greater than the maximum operating junction temperature. Continuous LOW and tTIMEOUT requirements. operation above the specifi ed maximum operation temperature may result in device degradation or failure. Operating junction temperature T
Note 10:
Specifi cations over the –5°C to 85°C operating ambient J (in °C) is calculated from the ambient temperature T temperature range are assured by design, characterization and correlation A and the average power dissipation P with statistical process controls. D (in watts) by the formula TJ = TA + θJA • PD. 4110fb 6