Datasheet ADE7978, ADE7933, ADE7932, ADE7923 (Analog Devices) - 10

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ADE7978/ADE7933/ADE7932/ADE7923 Data Sheet ADE7978 SPECIFICATIONS
VDD = 3.3 V ± 10%, GND = DGND = 0 V, XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C, TTYP = 25°C.
Table 2. Parameter1, 2 Min Typ Max Unit Test Conditions/Comments
CLOCK INPUT All specifications for CLKIN = 16.384 MHz Input Clock Frequency (CLKIN) 16.22 16.384 16.55 MHz Minimum = 16.384 MHz − 1%, maximum = 16.384 MHz + 1% XTALIN Logic Inputs Input High Voltage, V 2.4 V INH Input Low Voltage, V 0.8 V INL XTALIN Total Capacitance3 40 pF XTALOUT Total Capacitance3 40 pF CLOCK OUTPUT Output Clock Frequency at CLKOUT Pin 4.096 MHz Duty Cycle 50 % Output High Voltage, V 2.4 V OH I 4.8 mA SOURCE Output Low Voltage, V 0.4 V OL I 4.8 mA SINK LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS/HSA, DATA_A, DATA_B, DATA_C, DATA_N Input High Voltage, V 2.4 V VDD = 3.3 V ± 10% INH Input Current, I 2 40 nA Input = VDD = 3.3 V IN Input Low Voltage, V 0.8 V VDD = 3.3 V ± 10% INL Input Current, I 5 180 nA Input = 0 V, VDD = 3.3 V IN Input Capacitance, C 10 pF IN LOGIC INPUT—RESET Input High Voltage, V 2.4 V VDD = 3.3 V ± 10% INH Input Current, I 80 160 nA Input = VDD = 3.3 V IN Input Low Voltage, V 0.8 V VDD = 3.3 V ± 10% INL Input Current, I −8 +11 µA Input = 0 V, VDD = 3.3 V IN Input Capacitance, C 10 pF IN LOGIC OUTPUTS—IRQ0, IRQ1, MISO/HSD, VDD = 3.3 V ± 10% CLKOUT, SYNC, VT_A, VT_B, VT_C, VT_N, ZX/DREADY, RESET_ EN Output High Voltage, V 2.4 V VDD = 3.3 V OH I 4.8 mA SOURCE Output Low Voltage, V 0.4 V VDD = 3.3 V ± 10% OL I 4.8 mA SINK CF1, CF2, CF3/HSCLK Output High Voltage, V 2.4 V VDD = 3.3 V ± 10% OH I 8 mA SOURCE Output Low Voltage, V 0.4 V VDD = 3.3 V ± 10% OL I 8.5 mA SINK POWER SUPPLY For specified performance VDD Pin 2.97 3.63 V Minimum = 3.3 V − 10%, maximum = 3.3 V + 10% I 10.6 15.5 mA DD 1 See the Typical Performance Characteristics section. 2 See the Terminology section for a definition of the parameters. 3 XTALIN/XTALOUT total capacitances refer to the net capacitances on each pin. Each capacitance is the sum of the parasitic capacitance at the pin and the capacitance of the ceramic capacitor connected between the pin and GND. See the ADE7978, ADE7933/ADE7932, and ADE7923 Clocks section for more information. Rev. D | Page 10 of 125 Document Outline Features Applications Typical Application Circuit Revision History General Description Functional Block Diagrams Specifications System Specifications, ADE7978 and ADE7933/ADE7932/ADE7923 ADE7978 Specifications I2C Interface Timing Parameters SPI Interface Timing Parameters HSDC Interface Timing Parameters ADE7933/ADE7932 Specifications Regulatory Approvals Insulation and Safety Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics ADE7923 Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Total Energy Linearity over Supply and Temperature Fundamental Energy and RMS Linearity with Fifth Harmonic over Supply and Temperature Total Energy Error over Frequency RMS Linearity over Temperature and RMS Error over Frequency Energy Linearity Repeatability Cumulative Histograms of ADC Gain Temperature Coefficients Test Circuit Terminology Theory of Operation ADE7933/ADE7932/ADE7923 Analog Inputs Analog-to-Digital Conversion Oversampling Noise Shaping Antialiasing Filter ADC Transfer Function Untitled Current Channel ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling Voltage Channel ADCs Second Voltage Channel and Temperature Measurement Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling Changing the Phase Voltage Datapath Reference Circuits Phase Compensation Digital Signal Processor Power Quality Measurements Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection Sag Detection Level Setting Peak Detection Overvoltage and Overcurrent Detection Overvoltage Detection Overcurrent Detection Overvoltage and Overcurrent Level Setting Neutral Current Mismatch Root Mean Square Measurement Current RMS Calculation Current RMS Offset Compensation Voltage RMS Calculation Voltage RMS Offset Compensation Voltage RMS in Delta Configurations Active Power Calculation Total Active Power Calculation Fundamental Active Power Calculation Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire Configurations Line Cycle Active Energy Accumulation Mode Reactive Power Calculation Total Reactive Power Calculation Fundamental Reactive Power Calculation Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire Configurations Line Cycle Reactive Energy Accumulation Mode Apparent Power Calculation Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode BWATTHR and BFWATTHR Accumulation Register in 3-Phase, 3-Wire Configurations Line Cycle Apparent Energy Accumulation Mode Power Factor Calculation and Total Harmonic Distortion Calculation Power Factor Calculation Total Harmonic Distortion Calculation Waveform Sampling Mode Energy-to-Frequency Conversion TERMSELx[2:0] Bits CFxSEL[2:0] Bits Energy-to-Frequency Conversion Process Synchronizing Energy Registers with the CFx Outputs Energy Registers and CFx Outputs for Various Accumulation Modes Sign of Sum of Phase Powers in the CFx Datapath No Load Condition No Load Detection Based on Total Active and Reactive Powers No Load Detection Based on Fundamental Active and Reactive Powers No Load Detection Based on Apparent Power Interrupts Using the Interrupts with an MCU Power Management DC-to-DC Converter Magnetic Field Immunity Power-Up Procedure Initializing the Chipset Hardware Reset ADE7978/ADE7933/ADE7932 and ADE7923 Chipset Software Reset ADE7933/ADE7932 and ADE7923 Software Reset Low Power Mode Applications Information Differences Between the ADE7923 and the ADE7933/ADE7932 ADE7978, ADE7933/ADE7932 and ADE7923 in Polyphase Energy Meters ADE7978 Quick Setup as an Energy Meter Bit Stream Communication Between the ADE7978 and the ADE7933/ADE7932 and ADE7923 ADE7978, ADE7933/ADE7932, and ADE7923 Clocks Insulation Lifetime Layout Guidelines ADE7978 and ADE7933/ADE7932 Evaluation Board ADE7978 Die Version Serial Interfaces Serial Interface Selection Communication Verification I2C-Compatible Interface I2C Write Operation I2C Read Operation I2C Burst Read Operation SPI-Compatible Interface SPI Write Operation SPI Read Operation SPI Burst Read Operation HSDC Interface Checksum Register Register List Outline Dimensions Ordering Guide