Datasheet ADE7880 (Analog Devices) - 4

ADE7880 Data Sheet FUNCTIONAL BLOCK DIAGRAM RESET REFIN/OUT VDD AGND AVDD DVDD DGND 4 17 26 25 24 5 6 AIRMSOS POR LDO LDO 27 ADE7880 APGAIN CLKIN X2 AIRMS 2 PM0 27 LPF CLKOUT 28 3 PM1 1.2V REF HPFEN OF DIGITAL X2 AVRMS LPF CONFIG3 INTEGRATOR AIGAIN 27 CF1DEN IAP 7 PGA1 ADC HPF IAN 8 AVRMSOS DFC : 33 CF1 HPFEN OF APGAIN AWATTOS APHCAL CONFIG3 AVGAIN CF2DEN LPF VAP 23 PHASE A, PGA3 ADC PHASE B, HPF APGAIN AFWATTOS DFC AND : 34 CF2/HREADY PHASE C DATA COMPUTATIONAL CF3DEN IBP 9 BLOCK FOR PGA1 ADC TOTAL/FUNDAMENTAL ACTIVE ENERGIES FUNDAMENTAL APGAIN AFVAROS IBN 12 FUNDAMENTAL REACTIVE ENERGY ACTIVE AND APPARENT ENERGY REACTIVE POWER DFC : 35 CF3/HSCLK VOLTAGE CURRENT RMS HARMONIC INFORMATION CALCULATION VBP 22 FOR PHASE B PGA3 ADC (SEE PHASE A FOR DETAILED DATA PATH) COMPUTATIONAL 29 IRQ0 BLOCK FOR ICP 13 HARMONIC SPI/I2C PGA1 INFORMATION ON 32 IRQ1 ADC TOTAL/FUNDAMENTAL ACTIVE ENERGIES PHASE A CURRENT ICN 14 FUNDAMENTAL REACTIVE ENERGY APPARENT ENERGY AND VOLTAGE VOLTAGE/CURRENT RMS 36 SCLK/SCL HARMONIC INFORMATION CALCULATION VCP 19 FOR PHASE C PGA3 (SEE PHASE A FOR DETAILED DATA PATH) 38 MOSI/SDA ADC VN 18 I2C 37 MISO/HSD COMPUTATIONAL BLOCK FOR HARMONIC INFORMATION ON NEUTRAL CURRENT 39 SS/HSA HPFEN OF DIGITAL HSDC CONFIG3 INTEGRATOR NIGAIN NIRMSOS INP 15 DIGITAL SIGNAL PGA2 ADC X2 NIRMS HPF PROCESSOR INN 16 LPF
001 10193- Figure 1. ADE7880 Functional Block Diagram Rev. C | Page 4 of 107 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY POWER MANAGEMENT PSM0—NORMAL POWER MODE (ALL PARTS) PSM1—REDUCED POWER MODE PSM2—LOW POWER MODE PSM3—SLEEP MODE (ALL PARTS) POWER-UP PROCEDURE HARDWARE RESET SOFTWARE RESET FUNCTIONALITY THEORY OF OPERATION ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function CURRENT CHANNEL ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR VOLTAGE CHANNEL ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling CHANGING PHASE VOLTAGE DATA PATH POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection Sag Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch PHASE COMPENSATION REFERENCE CIRCUIT DIGITAL SIGNAL PROCESSOR ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Current Mean Absolute Value Calculation Current MAV Gain and Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS in 3-Phase, 3-Wire Delta Configurations ACTIVE POWER CALCULATION Total Active Power Calculation Fundamental Active Power Calculation Managing Change in Fundamental Line Frequency Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Active Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode FUNDAMENTAL REACTIVE POWER CALCULATION Fundamental Reactive Power Gain Calibration Fundamental Reactive Power Offset Calibration Sign of Fundamental Reactive Power Calculation Fundamental Reactive Energy Calculation Integration Time Under Steady Load Fundamental Reactive Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Apparent Energy Accumulation Modes Line Cycle Apparent Energy Accumulation Mode POWER FACTOR CALCULATION HARMONICS CALCULATIONS Harmonics Calcuations Theory Configuring the Harmonic Calculations Harmonic Calculations When a Phase is Monitored Harmonic Calculations When the Neutral is Monitored Configuring Harmonic Calculations Update Rate Recommended Approach to Managing Harmonic Calculations WAVEFORM SAMPLING MODE ENERGY-TO-FREQUENCY CONVERSION Synchronizing Energy Registers with CFx Outputs Energy Registers and CF Outputs for Various Accumulation Modes Sign of Sum of Phase Powers in the CFx Data Path NO LOAD CONDITION No Load Detection Based On Total Active Power and Apparent Power No Load Detection Based on Fundamental Active and Reactive Powers No Load Detection Based on Apparent Power CHECKSUM REGISTER INTERRUPTS Using the Interrupts with an MCU SERIAL INTERFACES Serial Interface Choice Communication Verification I2C-Compatible Interface I2C Write Operation I2C Read Operation I2C Read Operation of Harmonic Calculations Registers SPI-Compatible Interface SPI Read Operation SPI Read Operation of Harmonic Calculations Registers SPI Write Operation HSDC Interface ADE7880 QUICK SETUP AS ENERGY METER LAYOUT GUIDELINES CRYSTAL CIRCUIT ADE7880 EVALUATION BOARD DIE VERSION SILICON ANOMALY ADE7880 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADE7880 FUNCTIONALITY ISSUES REGISTERS LIST OUTLINE DIMENSIONS ORDERING GUIDE