Datasheet ADE7754 (Analog Devices) - 9

ADE7754 TERMINOLOGY AVDD Measurement Error
The error associated with the energy measurement made by the
5V 4V
ADE7754 is defined by the formula Percentage Error =  Energy gistered Re by ADE7754 − True Energy  × 100%
0V
 True Energy 
TIME Phase Error Between Channels POWER-ON
The HPF (high-pass filter) in the current channel has a phase
INACTIVE ACTIVE INACTIVE
lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is
RESET FLAG IN THE INTERRUPT
placed in the current channel. The phase correction network
STATUS REGISTER
ensures a phase match between the current channels and voltage
READ RSTATUS
channels to within ± 0.1° over a range of 45 Hz to 65 Hz and
REGISTER
±0.2° over a range of 40 Hz to 1 kHz. This phase mismatch Figure 4. On-Chip Power Supply Monitoring between the voltage and the current channels can be reduced The RESET bit in the interrupt status register is set to Logic 1 further with the phase calibration register in each phase. when AVDD drops below 4 V ± 5%. The RESET flag is always
Power Supply Rejection
masked by the interrupt enable register and cannot cause the This quantifies the ADE7754 measurement error as a percentage IRQ pin to go low. The power supply and decoupling for the of reading when power supplies are varied. For the ac PSR mea- part should ensure that the ripple at AVDD does not exceed 5 V surement, a reading at nominal supplies (5 V) is taken. A second ± 5% as specified for normal operation. reading is obtained using the same input signal levels when an ac (175 mV rms/100 Hz) signal is introduced onto the supplies. Any
ANALOG INPUTS
error introduced by this ac signal is expressed as a percentage of The ADE7754 has six analog inputs, divisible into two chan- reading. See the Measurement Error definition above. nels: current and voltage. The current channel consists of three For the dc PSR measurement, a reading at nominal supplies pairs of fully differential voltage inputs: IAP, IAN; IBP, IBN; and (5 V) is taken. A second reading is obtained using the same ICP, ICN. The fully differential voltage input pairs have a maxi- input signal levels when the power supplies are varied ± 5%. Any mum differential voltage of ± 0.5 V. The voltage channel has error introduced is again expressed as a percentage of reading. three single-ended voltage inputs: VAP, VBP, and VCP. These single-ended voltage inputs have a maximum input voltage of
ADC Offset Error
±0.5 V with respect to V This refers to the dc offset associated with the analog inputs to N. Both the current channel and the voltage channel have a PGA (programmable gain amplifier) with the ADCs. It means that with the analog inputs connected to possible gain selections of 1, 2, or 4. The same gain is applied to AGND, the ADCs still see a dc analog input signal. The magni- all the inputs of each channel. tude of the offset depends on the gain and input range selection (see the TPCs). However, when HPFs are switched on, the The gain selections are made by writing to the gain register. Bits 0 offset is removed from the current channels and the power and 1 select the gain for the PGA in the fully differential current calculation is unaffected by this offset. channel. The gain selection for the PGA in the single-ended volt- age channel is made via Bits 5 and 6. Figure 5 shows how a gain
Gain Error
selection for the current channel is made using the gain register. The gain error in the ADE7754 ADCs is defined as the differ- ence between the measured ADC output code (minus the
GAIN[7:0]
offset) and the ideal output code. See the Current Channel ADC and the Voltage Channel ADC sections. The difference is expressed as a percentage of the ideal code.
Gain Error Match GAIN (k) SELECTION
Gain error match is defined as the gain error (minus the offset)
IAP, IBP, ICP
obtained when switching between a gain of 1, 2, or 4. It is expressed as a percentage of the output ADC code obtained under a gain of 1.
VIN k VIN POWER SUPPLY MONITOR
The ADE7754 contains an on-chip power supply monitor. The analog supply (AV
IAN, IBN, ICN
DD) is continuously monitored by the ADE7754. If the supply is less than 4 V ± 5%, the ADE7754 goes into an inactive state (i.e., no energy is accumulated when the supply Figure 5. PGA in Current Channel voltage is below 4 V). This is useful to ensure correct device operation at power-up and during power-down. The power sup- ply monitor has built-in hysteresis and filtering, providing a high degree of immunity to false triggering due to noisy supplies. REV. 0 –9– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics TERMINOLOGY Measurement Error Phase Error Between Channels Power Supply Rejection ADC Offset Error Gain Error Gain Error Match POWER SUPPLY MONITOR ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialias Filter CURRENT CHANNEL ADC Current Channel ADC Gain Adjust Current Channel Sampling VOLTAGE CHANNEL ADC ZERO-CROSSING DETECTION Zero-Crossing Timeout PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG Level Set PEAK DETECTION Peak Level Set TEMPERATURE MEASUREMENT PHASE COMPENSATION ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Gain Adjust Current RMS Offset Compensation Voltage RMS Calculation Voltage RMS Gain Adjust Voltage RMS Offset Compensation ACTIVE POWER CALCULATION Power Offset Calibration Reverse Power Information TOTAL ACTIVE POWER CALCULATION ENERGY CALCULATION Integration Times Under Steady Load Energy to Frequency Conversion No Load Threshold Mode Selection of the Sum of the Three Active Energies LINE ENERGY ACCUMULATION REACTIVE POWER CALCULATION TOTAL REACTIVE POWER CALCULATION Reactive Energy Accumulation Selection APPARENT POWER CALCULATION Apparent Power Offset Calibration TOTAL APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Integration Times under Steady Load LINE APPARENT ENERGY ACCUMULATION ENERGIES SCALING CHECK SUM REGISTER SERIAL INTERFACE Serial Write Operation Serial Read Operation INTERRUPTS Using Interrupts with an MCU Interrupt Timing ACCESSING THE ADE7754 ON-CHIP REGISTERS Communications Register Operational Mode Register (0Ah) Gain Register (18h) CFNUM Register (25h) Measurement Mode Register (0Bh) Waveform Mode Register (0Ch) Watt Mode Register (0Dh) VA Mode Register (0Eh) Interrupt Enable Register (0Fh) Interrupt Status Register (10h)/Reset Interrupt Status Register (11h) OUTLINE DIMENSIONS