Datasheet LT1431 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Programmable Reference |
| Pages / Page | 14 / 6 — pin FuncTions. COLL (Pin 1):. RMID (Pin 7):. COMP (Pin 2):. REF (Pin 8):. … |
| File Format / Size | PDF / 233 Kb |
| Document Language | English |
pin FuncTions. COLL (Pin 1):. RMID (Pin 7):. COMP (Pin 2):. REF (Pin 8):. V+ (Pin 3):. RTOP (Pin 4):. GND-S (Pin 5):. CATHODE:. ANODE:
Model Line for this Datasheet
Text Version of Document
LT1431
pin FuncTions COLL (Pin 1):
Open collector of the output transistor. The
RMID (Pin 7):
Middle of the on-chip resistive divider string maximum pin voltage is 36V. The saturation voltage at between RTOP and GND-S. The pin is tied to REF for self- 100mA is approximately 1V. contained 5V operation. It may be left open if unused.
COMP (Pin 2):
Base of the driver for the output transis-
REF (Pin 8):
Control pin of the shunt regulator with a tor. This pin allows additional compensation for complex 2.5V threshold. If V+ > 3V, input bias current cancellation feedback systems and shutdown of the regulator. It must reduces IB to 0.2µA typical. be left open if unused. COMP, RTOP, RMID, and REF have static discharge protection
V+ (Pin 3):
Bias voltage for the entire shunt regulator. circuits that must not be activated on a continuous basis. The maximum input voltage is 36V and the minimum to Therefore, the absolute maximum DC voltage on these operate is equal to VREF (2.5V). The quiescent current is pins is 6V, well beyond the normal operating conditions. typically 0.6mA. As with all bipolar ICs, the LT1431 contains parasitic diodes
RTOP (Pin 4):
Top of the on-chip 5k-5k resistive divider which must not be forward biased or else anomalous that guarantees 1% accuracy of operation as a 5V shunt behavior will result. Pin conditions to be avoided are RTOP regulator with no external trim. The pin is tied to COLL for below RMID in voltage and any pin below GND-F in voltage self-contained 5V operation. It may be left open if unused. (except for GND-S). See note on parasitic diodes below. The following pin definitions apply to the Z package.
GND-S (Pin 5):
Ground reference for the on-chip resis-
CATHODE:
Corresponds to COLL and V+ tied together. tive divider and shunt regulator circuitry except for the output transistor. This pin allows external current limit
ANODE:
Corresponds to GND-S and GND-F tied together. of the output transistor with one resistor between GND-F
REF:
Corresponds to REF. (force) and GND-S (sense).
GND-F (Pin 6):
Emitter of the output transistor and sub- strate connection for the die.
block DiagraM
RTOP V+ COMP COLLECTOR 4 3 2 1 5k 8 REF + gm = 4mA/V 7 RMID – 5k 2.5V LT1431 BD 5 6 GND-SENSE GND-FORCE 1431fe 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Schematic Diagram Package Description Revision History Package Description Related Parts
pin FuncTions COLL (Pin 1):
Open collector of the output transistor. The
RMID (Pin 7):
Middle of the on-chip resistive divider string maximum pin voltage is 36V. The saturation voltage at between RTOP and GND-S. The pin is tied to REF for self- 100mA is approximately 1V. contained 5V operation. It may be left open if unused.
COMP (Pin 2):
Base of the driver for the output transis-
REF (Pin 8):
Control pin of the shunt regulator with a tor. This pin allows additional compensation for complex 2.5V threshold. If V+ > 3V, input bias current cancellation feedback systems and shutdown of the regulator. It must reduces IB to 0.2µA typical. be left open if unused. COMP, RTOP, RMID, and REF have static discharge protection
V+ (Pin 3):
Bias voltage for the entire shunt regulator. circuits that must not be activated on a continuous basis. The maximum input voltage is 36V and the minimum to Therefore, the absolute maximum DC voltage on these operate is equal to VREF (2.5V). The quiescent current is pins is 6V, well beyond the normal operating conditions. typically 0.6mA. As with all bipolar ICs, the LT1431 contains parasitic diodes
RTOP (Pin 4):
Top of the on-chip 5k-5k resistive divider which must not be forward biased or else anomalous that guarantees 1% accuracy of operation as a 5V shunt behavior will result. Pin conditions to be avoided are RTOP regulator with no external trim. The pin is tied to COLL for below RMID in voltage and any pin below GND-F in voltage self-contained 5V operation. It may be left open if unused. (except for GND-S). See note on parasitic diodes below. The following pin definitions apply to the Z package.
GND-S (Pin 5):
Ground reference for the on-chip resis-
CATHODE:
Corresponds to COLL and V+ tied together. tive divider and shunt regulator circuitry except for the output transistor. This pin allows external current limit
ANODE:
Corresponds to GND-S and GND-F tied together. of the output transistor with one resistor between GND-F
REF:
Corresponds to REF. (force) and GND-S (sense).
GND-F (Pin 6):
Emitter of the output transistor and sub- strate connection for the die.
block DiagraM
RTOP V+ COMP COLLECTOR 4 3 2 1 5k 8 REF + gm = 4mA/V 7 RMID – 5k 2.5V LT1431 BD 5 6 GND-SENSE GND-FORCE 1431fe 6 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Schematic Diagram Package Description Revision History Package Description Related Parts
