Datasheet LTC7821 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Hybrid Step-Down Synchronous Controller |
| Pages / Page | 36 / 9 — PIN FUNCTIONS MODE/PLLIN (Pin 1):. CLKOUT (Pin 2):. TRACK/SS (Pin 7):. … |
| Revision | A |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
PIN FUNCTIONS MODE/PLLIN (Pin 1):. CLKOUT (Pin 2):. TRACK/SS (Pin 7):. RUN (Pin 3):. FAULT (Pin 4):. EXT_REF (Pin 8):
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Text Version of Document
LTC7821
PIN FUNCTIONS MODE/PLLIN (Pin 1):
Mode Selection or External Synchro- the capacitor balancing phase. It also sets the auto-retry nization Input to Phase Detector. When external synchro- timeout, should the capacitors fail to reach this voltage nization is not used, this pin selects the operating modes within the set time. Capacitors CFLY and CMID begin and and can be tied to SGND, to INTVCC or left floating. If the end charging when the TIMER voltage is between 0.5V pin is connected to SGND, it enables forced continuous and 1.2V, respectively. If the capacitor is balanced before mode while a connection to INTVCC enables pulse-skipping the TIMER voltage reaches 1.2V, this voltage is reset to mode. Floating the pin enables Burst Mode operation. ground and normal operation begins. However, if the bal- For external sync, apply a clock signal to this pin. The ance is not reached when the voltage reaches 1.2V, then integrated PLL along with its internal compensation net- the charging of the capacitors stops and the auto-retry work will synchronize the internal oscillator to this clock. timeout period begins. The TIMER capacitor will now slew Forced continuous mode will be enabled. at half the rate until it reaches 4V and then resets to zero and begins to slew at 1x rate. Once it reaches 0.5V, the CFLY
CLKOUT (Pin 2):
Clock Output Pin. This pin outputs a and CMID begin to charge again and the process repeats. clock 180° out of phase with the main operating clock of the LTC7821.
TRACK/SS (Pin 7):
Output Voltage Tracking and Soft-Start Input. The LTC7821 regulates the VFB voltage to the lowest
RUN (Pin 3):
Run Control Input. A voltage above 1.3V of three voltages: 0.8V, the voltage on the EXT_REF pin or turns the controller ON. There is a 1μA pull-up current the voltage on the TRACK/SS pin. An internal 10μA pull- on this pin when its voltage is below 1.3V. up current source is connected to this pin. A capacitor to
FAULT (Pin 4):
Open Drain Output pin. When the signal ground at this pin sets the ramp time to the final regulated goes low, it indicates one of the following conditions: output voltage. Alternatively, a resistor divider from another voltage supply connected to this pin allows the LTC7821 (a) In the capacitor balancing phase, capacitors CFLY or output voltage to track the other supply during start-up. CMID (see Typical Application) are not charged to VIN/2. A low FAULT indicates an abnormal condition
EXT_REF (Pin 8):
External Reference Input. A voltage ap- that is preventing CFLY or CMID from being be charged plied to this pin forces the VFB to regulate to this voltage. up to VIN/2. Internal clamps set at 0.4V and 0.93V limit the lower and (b) During normal operation, the voltage deviates from upper bounds of VFB regulation. Connecting this pin to V INTVCC will cause the internal reference to be used for IN/2 by a window amount set by the voltage on the HYS_PRGM pin. output voltage regulation. (c) The die temperature exceeds its internally set limit or
HYS_PRGM (Pin 9):
There is a 10μA current flowing out the PTC resistor connected as the lower leg of a resistor of this pin. A voltage created by connecting a resistor divider trips the TEMP pin threshold. from this pin to ground sets an equal amount of window threshold around VIN/2 to a window comparator. When the During any of these condition, the TRACK/SS pin will also voltage at MIDSENSE is not within this window threshold, be pulled low. FAULT will be pulled low and switching will stop. CFLY and
PGOOD (Pin 5):
Power Good Pin. This is an open drain CMID will be rebalanced to half of VIN before resuming output. PGOOD is pulled to ground when the voltage of normal operation. the VFB pin is not within ±7.5% of its set point after an
ITH (Pin 10):
Current Control Threshold and Error Amplifier internal 50μs mask timer expires. It will also be pulled low Compensation Point. The current comparator threshold when FAULT is tripped. increases with its ITH control voltage.
TIMER (Pin 6):
Charge Balancing Timer Input. A capaci-
FREQ (Pin 11):
Frequency Set Pin. There is a 10μA current tor connected from this pin to ground sets the amount flowing out of this pin. A resistor to ground sets a voltage of time allocated to charge CFLY and CMID to VIN/2 during which in turn programs the frequency. Rev A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts
PIN FUNCTIONS MODE/PLLIN (Pin 1):
Mode Selection or External Synchro- the capacitor balancing phase. It also sets the auto-retry nization Input to Phase Detector. When external synchro- timeout, should the capacitors fail to reach this voltage nization is not used, this pin selects the operating modes within the set time. Capacitors CFLY and CMID begin and and can be tied to SGND, to INTVCC or left floating. If the end charging when the TIMER voltage is between 0.5V pin is connected to SGND, it enables forced continuous and 1.2V, respectively. If the capacitor is balanced before mode while a connection to INTVCC enables pulse-skipping the TIMER voltage reaches 1.2V, this voltage is reset to mode. Floating the pin enables Burst Mode operation. ground and normal operation begins. However, if the bal- For external sync, apply a clock signal to this pin. The ance is not reached when the voltage reaches 1.2V, then integrated PLL along with its internal compensation net- the charging of the capacitors stops and the auto-retry work will synchronize the internal oscillator to this clock. timeout period begins. The TIMER capacitor will now slew Forced continuous mode will be enabled. at half the rate until it reaches 4V and then resets to zero and begins to slew at 1x rate. Once it reaches 0.5V, the CFLY
CLKOUT (Pin 2):
Clock Output Pin. This pin outputs a and CMID begin to charge again and the process repeats. clock 180° out of phase with the main operating clock of the LTC7821.
TRACK/SS (Pin 7):
Output Voltage Tracking and Soft-Start Input. The LTC7821 regulates the VFB voltage to the lowest
RUN (Pin 3):
Run Control Input. A voltage above 1.3V of three voltages: 0.8V, the voltage on the EXT_REF pin or turns the controller ON. There is a 1μA pull-up current the voltage on the TRACK/SS pin. An internal 10μA pull- on this pin when its voltage is below 1.3V. up current source is connected to this pin. A capacitor to
FAULT (Pin 4):
Open Drain Output pin. When the signal ground at this pin sets the ramp time to the final regulated goes low, it indicates one of the following conditions: output voltage. Alternatively, a resistor divider from another voltage supply connected to this pin allows the LTC7821 (a) In the capacitor balancing phase, capacitors CFLY or output voltage to track the other supply during start-up. CMID (see Typical Application) are not charged to VIN/2. A low FAULT indicates an abnormal condition
EXT_REF (Pin 8):
External Reference Input. A voltage ap- that is preventing CFLY or CMID from being be charged plied to this pin forces the VFB to regulate to this voltage. up to VIN/2. Internal clamps set at 0.4V and 0.93V limit the lower and (b) During normal operation, the voltage deviates from upper bounds of VFB regulation. Connecting this pin to V INTVCC will cause the internal reference to be used for IN/2 by a window amount set by the voltage on the HYS_PRGM pin. output voltage regulation. (c) The die temperature exceeds its internally set limit or
HYS_PRGM (Pin 9):
There is a 10μA current flowing out the PTC resistor connected as the lower leg of a resistor of this pin. A voltage created by connecting a resistor divider trips the TEMP pin threshold. from this pin to ground sets an equal amount of window threshold around VIN/2 to a window comparator. When the During any of these condition, the TRACK/SS pin will also voltage at MIDSENSE is not within this window threshold, be pulled low. FAULT will be pulled low and switching will stop. CFLY and
PGOOD (Pin 5):
Power Good Pin. This is an open drain CMID will be rebalanced to half of VIN before resuming output. PGOOD is pulled to ground when the voltage of normal operation. the VFB pin is not within ±7.5% of its set point after an
ITH (Pin 10):
Current Control Threshold and Error Amplifier internal 50μs mask timer expires. It will also be pulled low Compensation Point. The current comparator threshold when FAULT is tripped. increases with its ITH control voltage.
TIMER (Pin 6):
Charge Balancing Timer Input. A capaci-
FREQ (Pin 11):
Frequency Set Pin. There is a 10μA current tor connected from this pin to ground sets the amount flowing out of this pin. A resistor to ground sets a voltage of time allocated to charge CFLY and CMID to VIN/2 during which in turn programs the frequency. Rev A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts
