Datasheet LTC3895 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 150V Low IQ, Synchronous Step-Down DC/DC Controller |
| Pages / Page | 38 / 9 — pin FuncTions OVLO (Pin 1):. ITH (Pin 7):. MODE (Pin 8):. VPRG (Pin 2):. … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
pin FuncTions OVLO (Pin 1):. ITH (Pin 7):. MODE (Pin 8):. VPRG (Pin 2):. GND (Pins 9, 12, 15, Exposed Pin 39):. SENSE+ (Pin 3):
Model Line for this Datasheet
Text Version of Document
LTC3895
pin FuncTions OVLO (Pin 1):
Overvoltage Lockout Input. A voltage on
ITH (Pin 7):
Error Amplifier Output and Switching Regulator this pin above 1.2V disables switching of the controller. Compensation Point. The current comparator trip point The DRVCC and INTVCC supplies maintain regulation during increases with this control voltage. an OVLO event. Exceeding the OVLO threshold triggers a
MODE (Pin 8):
Mode Select and Burst Clamp Adjust In- soft-start reset. If the OVLO function is not used, connect put. This input determines how the LTC3895 operates at this pin to GND. light loads. Pulling this pin to ground selects Burst Mode
VPRG (Pin 2):
Output Voltage Control Pin. This pin sets operation with the burst clamp level defaulting to 25% of the regulator in adjustable output mode using external VSENSE(MAX). Tying this pin to a voltage between 0.5V and feedback resistors or fixed 5V/3.3V output mode. Floating 1.0V selects Burst Mode operation and adjusts the burst this pin allows the output to be programmed from 0.8V clamp between 10% and 60%. Tying this pin to INTVCC to 60V with an external resistor divider on the VFB pin, forces continuous inductor current operation. Tying this pin regulating VFB to 0.8V. Tying this pin to INTVCC or GND to a voltage greater than 1.4V and less than INTVCC – 1.3V programs the output to 5V or 3.3V, respectively, through selects pulse-skipping operation. an internal resistor divider on VFB.
GND (Pins 9, 12, 15, Exposed Pin 39):
Ground. All GND
SENSE+ (Pin 3):
The (+) Input to the Differential Current pins must be tied together for operation. The exposed pad Comparator. The ITH pin voltage and controlled offsets must be soldered to PCB ground for rated electrical and between the SENSE– and SENSE+ pins in conjunction with thermal performance. RSENSE set the current trip threshold.
CPUMP_EN (Pin 10):
Charge Pump Enable Pin for the Top
SENSE– (Pin 4):
The (–) Input to the Differential Current Gate Driver Boost Supply. Tying this pin to INTVCC enables Comparator. When SENSE– is greater than INTVCC, the the boost supply charge pump and allows for 100% duty SENSE– pin supplies power to the current comparator. cycle operation in dropout. Tying this pin to GND disables
SS (Pin 5):
Soft-Start Input. The LTC3895 regulates the the charge pump and enables boost refresh, allowing for V 99% duty cycle operation in dropout. Do not float this pin. FB voltage to the smaller of 0.8V or the voltage on the SS pin. An internal 10μA pull-up current source is con-
CLKOUT (Pin 11):
Output Clock Signal. This signal is nected to this pin. A capacitor to ground at this pin sets available to daisy-chain other controller ICs for additional the ramp time to final regulated output voltage. The SS MOSFET driver stages/phases. The output levels swing pin is also used for the Regulator Shutdown (REGSD) from INTVCC to ground. feature. A 5μA/1μA pull-down current can be connected
PLLIN (Pin 13):
External Synchronization Input to Phase on SS depending on the state of the EXTVCC LDO and the Detector. When an external clock is applied to this pin, voltage on SS. See Regulator Shutdown in the Operation the phase-locked loop will force the rising TG signal to be section for more information. To defeat the REGSD feature, synchronized with the rising edge of the external clock. If place a 330k or smaller resistor between INTVCC and SS. the MODE pin is set to Forced Continuous Mode or Burst See Soft-Start Pin in the Applications Information section Mode operation, then the regulator operates in Forced for more information on defeating REGSD. Continuous Mode when synchronized. If the MODE pin is
VFB (Pin 6):
Feedback Input. If the VPRG pin is floating, set to pulse-skipping mode, then the regulator operates the VFB pin receives the remotely sensed feedback volt- in pulse-skipping mode when synchronized. age from an eternal resistor divider across the output. If
PGOOD (Pin 14):
Open-Drain Logic Output. PGOOD is VPRG is tied to GND or INTVCC, the VFB pin receives the pulled to ground when the voltage on the V remotely sensed output voltage directly. FB pin is not within ±10% of its set point.
NC (Pin 16):
No connect. Float this pin or connect to GND. 3895fa For more information www.linear.com/LTC3895 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions OVLO (Pin 1):
Overvoltage Lockout Input. A voltage on
ITH (Pin 7):
Error Amplifier Output and Switching Regulator this pin above 1.2V disables switching of the controller. Compensation Point. The current comparator trip point The DRVCC and INTVCC supplies maintain regulation during increases with this control voltage. an OVLO event. Exceeding the OVLO threshold triggers a
MODE (Pin 8):
Mode Select and Burst Clamp Adjust In- soft-start reset. If the OVLO function is not used, connect put. This input determines how the LTC3895 operates at this pin to GND. light loads. Pulling this pin to ground selects Burst Mode
VPRG (Pin 2):
Output Voltage Control Pin. This pin sets operation with the burst clamp level defaulting to 25% of the regulator in adjustable output mode using external VSENSE(MAX). Tying this pin to a voltage between 0.5V and feedback resistors or fixed 5V/3.3V output mode. Floating 1.0V selects Burst Mode operation and adjusts the burst this pin allows the output to be programmed from 0.8V clamp between 10% and 60%. Tying this pin to INTVCC to 60V with an external resistor divider on the VFB pin, forces continuous inductor current operation. Tying this pin regulating VFB to 0.8V. Tying this pin to INTVCC or GND to a voltage greater than 1.4V and less than INTVCC – 1.3V programs the output to 5V or 3.3V, respectively, through selects pulse-skipping operation. an internal resistor divider on VFB.
GND (Pins 9, 12, 15, Exposed Pin 39):
Ground. All GND
SENSE+ (Pin 3):
The (+) Input to the Differential Current pins must be tied together for operation. The exposed pad Comparator. The ITH pin voltage and controlled offsets must be soldered to PCB ground for rated electrical and between the SENSE– and SENSE+ pins in conjunction with thermal performance. RSENSE set the current trip threshold.
CPUMP_EN (Pin 10):
Charge Pump Enable Pin for the Top
SENSE– (Pin 4):
The (–) Input to the Differential Current Gate Driver Boost Supply. Tying this pin to INTVCC enables Comparator. When SENSE– is greater than INTVCC, the the boost supply charge pump and allows for 100% duty SENSE– pin supplies power to the current comparator. cycle operation in dropout. Tying this pin to GND disables
SS (Pin 5):
Soft-Start Input. The LTC3895 regulates the the charge pump and enables boost refresh, allowing for V 99% duty cycle operation in dropout. Do not float this pin. FB voltage to the smaller of 0.8V or the voltage on the SS pin. An internal 10μA pull-up current source is con-
CLKOUT (Pin 11):
Output Clock Signal. This signal is nected to this pin. A capacitor to ground at this pin sets available to daisy-chain other controller ICs for additional the ramp time to final regulated output voltage. The SS MOSFET driver stages/phases. The output levels swing pin is also used for the Regulator Shutdown (REGSD) from INTVCC to ground. feature. A 5μA/1μA pull-down current can be connected
PLLIN (Pin 13):
External Synchronization Input to Phase on SS depending on the state of the EXTVCC LDO and the Detector. When an external clock is applied to this pin, voltage on SS. See Regulator Shutdown in the Operation the phase-locked loop will force the rising TG signal to be section for more information. To defeat the REGSD feature, synchronized with the rising edge of the external clock. If place a 330k or smaller resistor between INTVCC and SS. the MODE pin is set to Forced Continuous Mode or Burst See Soft-Start Pin in the Applications Information section Mode operation, then the regulator operates in Forced for more information on defeating REGSD. Continuous Mode when synchronized. If the MODE pin is
VFB (Pin 6):
Feedback Input. If the VPRG pin is floating, set to pulse-skipping mode, then the regulator operates the VFB pin receives the remotely sensed feedback volt- in pulse-skipping mode when synchronized. age from an eternal resistor divider across the output. If
PGOOD (Pin 14):
Open-Drain Logic Output. PGOOD is VPRG is tied to GND or INTVCC, the VFB pin receives the pulled to ground when the voltage on the V remotely sensed output voltage directly. FB pin is not within ±10% of its set point.
NC (Pin 16):
No connect. Float this pin or connect to GND. 3895fa For more information www.linear.com/LTC3895 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
