Datasheet LTC3874 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | PolyPhase Step-Down Synchronous Slave Controller with Sub-Milliohm DCR Sensing |
| Pages / Page | 30 / 7 — PIN FUNCTIONS MODE0/MODE1 (PIN 1/Pin 8):. BOOST0/BOOST1 (Pin 22/Pin 16):. … |
| File Format / Size | PDF / 919 Kb |
| Document Language | English |
PIN FUNCTIONS MODE0/MODE1 (PIN 1/Pin 8):. BOOST0/BOOST1 (Pin 22/Pin 16):. SENSE0 /ISENSE1 (Pin 2/Pin 7):
Model Line for this Datasheet
Text Version of Document
LTC3874
PIN FUNCTIONS MODE0/MODE1 (PIN 1/Pin 8):
DCM/CCM Mode Control source. Voltage swing at the pins are from a Schottky pins. Each channel runs in forced continuous mode if the diode (external) voltage drop below ground to VIN. Mode pin is logic high. There is an internal 500k pull-down
BOOST0/BOOST1 (Pin 22/Pin 16):
Boosted Floating Driver resistor on Mode pin. To select discontinuous conduction Supplies. The (+) terminal of the bootstrap capacitors con- mode, float or pull down the MODE pin. nect to these pins. These pins swing from a diode voltage
I + + SENSE0 /ISENSE1 (Pin 2/Pin 7):
Current Sense Compara- drop below INTVCC up to VIN + INTVCC. tor Inputs. The (+) inputs to the current comparators are
BG0/BG1 (Pin 21/Pin 17):
Bottom Gate Driver Outputs. normally connected to DCR sensing networks. These pins drive the gates of the bottom N-channel MOS-
I − − SENSE0 /ISENSE1 (Pin 3/Pin 6):
Current Sense Compara- FETs between GND and INTVCC. tor Inputs. The (−) inputs to the current comparators are
EXTV
connected to the outputs.
CC (Pin 18):
External Power Input to an Internal Switch Connected to INTVCC. The switch closes and supplies the
RUN0/RUN1 (Pin 4/Pin 5):
Enable Run Inputs. Logic high IC power, bypassing the internal low dropout regulator, on RUN pin enables the corresponding channel. whenever EXTVCC is higher than 4.7V and VIN is greater
I
than 7V. Do not exceed 6V on this pin.
TH0/ITH1 (Pin 28/Pin 9):
Current Control Threshold. Each associated channel’s current comparator tripping threshold
INTVCC (Pin 19):
Internal 5.5V Regulator Output. The con- increases with its ITH voltage. These pins must be con- trol circuits are powered from this voltage. Decouple this nected to the master controller’s ITH pins. pin to GND with a minimum of 4.7μF low ESR tantalum
FREQ (Pin 10):
Frequency Set Pin. There is a precision or ceramic capacitor. 10µA current flowing out of this pin. A resistor to ground
VIN (Pin 20):
Main Input Supply. Decouple this pin to GND sets a voltage which in turn programs the frequency. This with a capacitor (0.1μF to 1μF). pin sets the default switching frequency when there is no
FAULT0, FAULT1 (Pin 26/Pin 25):
Master Controller Fault external clock on the SYNC pin. See the application section Inputs. Connect these pins to the master chip fault indica- for detailed information. tor pins to respond to the fault signals from the master
ILIM (Pin 11):
Current Comparators Sense Voltage Limit. controller. When a FAULT pin is floating or low, both TG Program a DC voltage at this pin to set the maximum cur- and BG pins are pulled down in the corresponding chan- rent sense threshold for the current comparators. nel. There is an internal 500k pull-down resistor on each
SYNC (Pin 12):
External Clock Synchronization Input. If an FAULT pin. external clock is present at this pin, the switching frequency
LOWDCR (Pin 27):
Sub-milliohm DCR Current Sensing will be synchronized to the
falling edge
of external clock. Enable Pin. There is an internal 500k pull-up resistor be- Tie this pin to GND if not used. tween LOWDCR pin and INTVCC. Floating or pulling this
PHASMD (Pin 13):
Phase Set Pin. This pin determines the pin logic high will enable the sub-milliohm DCR current relative phases between the external clock on pin SYNC sensing. Puling this pin logic low will disable the sub- and the internal controllers. See Table 1 in the Operation milliohm DCR current sensing. section for details.
GND (Exposed Pad Pin 29):
Ground. Connect this pad,
TG0/TG1 (Pin 24/Pin 14):
Top Gate Driver Outputs. These through vias, to a solid ground plane under the circuit. are the outputs of floating drivers with a voltage swing The sources of the bottom N-channel MOSFETs, the (–) equal to INTV terminal of CINTVCC, and the (–) terminal of CIN should CC superimposed on the switch node voltages. connect to this ground plane as closely as possible to
SW0/SW1 (Pin 23/Pin 15):
Switch Node Connections. the IC. All small-signal components and compensation Connect these pins to the output filter inductor, bottom components should also connect to this ground plane. N-channel MOSFET drain and top N-channel MOSFET 3874fb For more information www.linear.com/LTC3874 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Operation Applications Information Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS MODE0/MODE1 (PIN 1/Pin 8):
DCM/CCM Mode Control source. Voltage swing at the pins are from a Schottky pins. Each channel runs in forced continuous mode if the diode (external) voltage drop below ground to VIN. Mode pin is logic high. There is an internal 500k pull-down
BOOST0/BOOST1 (Pin 22/Pin 16):
Boosted Floating Driver resistor on Mode pin. To select discontinuous conduction Supplies. The (+) terminal of the bootstrap capacitors con- mode, float or pull down the MODE pin. nect to these pins. These pins swing from a diode voltage
I + + SENSE0 /ISENSE1 (Pin 2/Pin 7):
Current Sense Compara- drop below INTVCC up to VIN + INTVCC. tor Inputs. The (+) inputs to the current comparators are
BG0/BG1 (Pin 21/Pin 17):
Bottom Gate Driver Outputs. normally connected to DCR sensing networks. These pins drive the gates of the bottom N-channel MOS-
I − − SENSE0 /ISENSE1 (Pin 3/Pin 6):
Current Sense Compara- FETs between GND and INTVCC. tor Inputs. The (−) inputs to the current comparators are
EXTV
connected to the outputs.
CC (Pin 18):
External Power Input to an Internal Switch Connected to INTVCC. The switch closes and supplies the
RUN0/RUN1 (Pin 4/Pin 5):
Enable Run Inputs. Logic high IC power, bypassing the internal low dropout regulator, on RUN pin enables the corresponding channel. whenever EXTVCC is higher than 4.7V and VIN is greater
I
than 7V. Do not exceed 6V on this pin.
TH0/ITH1 (Pin 28/Pin 9):
Current Control Threshold. Each associated channel’s current comparator tripping threshold
INTVCC (Pin 19):
Internal 5.5V Regulator Output. The con- increases with its ITH voltage. These pins must be con- trol circuits are powered from this voltage. Decouple this nected to the master controller’s ITH pins. pin to GND with a minimum of 4.7μF low ESR tantalum
FREQ (Pin 10):
Frequency Set Pin. There is a precision or ceramic capacitor. 10µA current flowing out of this pin. A resistor to ground
VIN (Pin 20):
Main Input Supply. Decouple this pin to GND sets a voltage which in turn programs the frequency. This with a capacitor (0.1μF to 1μF). pin sets the default switching frequency when there is no
FAULT0, FAULT1 (Pin 26/Pin 25):
Master Controller Fault external clock on the SYNC pin. See the application section Inputs. Connect these pins to the master chip fault indica- for detailed information. tor pins to respond to the fault signals from the master
ILIM (Pin 11):
Current Comparators Sense Voltage Limit. controller. When a FAULT pin is floating or low, both TG Program a DC voltage at this pin to set the maximum cur- and BG pins are pulled down in the corresponding chan- rent sense threshold for the current comparators. nel. There is an internal 500k pull-down resistor on each
SYNC (Pin 12):
External Clock Synchronization Input. If an FAULT pin. external clock is present at this pin, the switching frequency
LOWDCR (Pin 27):
Sub-milliohm DCR Current Sensing will be synchronized to the
falling edge
of external clock. Enable Pin. There is an internal 500k pull-up resistor be- Tie this pin to GND if not used. tween LOWDCR pin and INTVCC. Floating or pulling this
PHASMD (Pin 13):
Phase Set Pin. This pin determines the pin logic high will enable the sub-milliohm DCR current relative phases between the external clock on pin SYNC sensing. Puling this pin logic low will disable the sub- and the internal controllers. See Table 1 in the Operation milliohm DCR current sensing. section for details.
GND (Exposed Pad Pin 29):
Ground. Connect this pad,
TG0/TG1 (Pin 24/Pin 14):
Top Gate Driver Outputs. These through vias, to a solid ground plane under the circuit. are the outputs of floating drivers with a voltage swing The sources of the bottom N-channel MOSFETs, the (–) equal to INTV terminal of CINTVCC, and the (–) terminal of CIN should CC superimposed on the switch node voltages. connect to this ground plane as closely as possible to
SW0/SW1 (Pin 23/Pin 15):
Switch Node Connections. the IC. All small-signal components and compensation Connect these pins to the output filter inductor, bottom components should also connect to this ground plane. N-channel MOSFET drain and top N-channel MOSFET 3874fb For more information www.linear.com/LTC3874 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Operation Applications Information Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
