Datasheet LT3437 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | High Voltage 500mA, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current |
| Pages / Page | 28 / 8 — PI FU CTIO S (DD/FE). SW (Pin 1/Pin 2):. GND (Pins 4, 11/Pins 8, 17):. NC … |
| File Format / Size | PDF / 573 Kb |
| Document Language | English |
PI FU CTIO S (DD/FE). SW (Pin 1/Pin 2):. GND (Pins 4, 11/Pins 8, 17):. NC (Pins 1, 3, 5, 7, 13, 16)(FE Package ONLY):
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Text Version of Document
LT3437
U U U PI FU CTIO S (DD/FE) SW (Pin 1/Pin 2):
The SW pin is the emitter of the on-chip and its voltage loss approximates that of a 0.8Ω FET power NPN switch. This pin is driven up to the input pin structure. voltage during switch on time. Inductor current drives the
GND (Pins 4, 11/Pins 8, 17):
The GND pin connection SW pin negative during switch off time. Negative voltage acts as the reference for the regulated output, so load is clamped with an external schottky catch diode to pre- regulation will suffer if the “ground” end of the load is not vent excessive negative voltages. at the same voltage as the GND pin of the IC. This
NC (Pins 1, 3, 5, 7, 13, 16)(FE Package ONLY):
condition will occur when load current or other currents No Connection. The NC pins are electrically isolated from flow through metal paths between the GND pin and the the LT3437. The NC pins may be connected to PCB traces load ground. Keep the path between the GND pin and the to aid PCB layout. load ground short and use a ground plane when possible. The GND pin also acts as a heat sink and should be
VIN (Pin 2/Pin 4):
This is the collector of the on-chip power soldered (along with the exposed leadframe) to the cop- NPN switch. VIN powers the internal control circuitry when per ground plane to reduce thermal resistance (see Appli- a voltage on the BIAS pin is not present. High di/dt edges cations Information). occur on this pin during switch turn on and off. Keep the path short from the VIN pin through the input bypass
CSS (Pin 5/Pin 9):
A capacitor from the CSS pin to the capacitor, through the catch diode back to SW. All trace regulated output voltage determines the output voltage inductance on this path will create a voltage spike at switch ramp rate during start-up. When the current through the off, adding to the VCE voltage across the internal NPN. CSS capacitor exceeds the CSS threshold (ICSS), the volt- age ramp of the output is limited. The CSS threshold is
BOOST (Pin 3/Pin 6):
The BOOST pin is used to provide a proportional to the FB voltage (see Typical Performance drive voltage, higher than the input voltage, to the internal Characteristics) and is defeated for FB voltage greater than bipolar NPN power switch. Without this added voltage, the 0.9V (typical). See Soft-Start section in Applications Infor- typical switch voltage loss would be about 1.5V. The mation for details. additional BOOST voltage allows the switch to saturate 3437fc 8
U U U PI FU CTIO S (DD/FE) SW (Pin 1/Pin 2):
The SW pin is the emitter of the on-chip and its voltage loss approximates that of a 0.8Ω FET power NPN switch. This pin is driven up to the input pin structure. voltage during switch on time. Inductor current drives the
GND (Pins 4, 11/Pins 8, 17):
The GND pin connection SW pin negative during switch off time. Negative voltage acts as the reference for the regulated output, so load is clamped with an external schottky catch diode to pre- regulation will suffer if the “ground” end of the load is not vent excessive negative voltages. at the same voltage as the GND pin of the IC. This
NC (Pins 1, 3, 5, 7, 13, 16)(FE Package ONLY):
condition will occur when load current or other currents No Connection. The NC pins are electrically isolated from flow through metal paths between the GND pin and the the LT3437. The NC pins may be connected to PCB traces load ground. Keep the path between the GND pin and the to aid PCB layout. load ground short and use a ground plane when possible. The GND pin also acts as a heat sink and should be
VIN (Pin 2/Pin 4):
This is the collector of the on-chip power soldered (along with the exposed leadframe) to the cop- NPN switch. VIN powers the internal control circuitry when per ground plane to reduce thermal resistance (see Appli- a voltage on the BIAS pin is not present. High di/dt edges cations Information). occur on this pin during switch turn on and off. Keep the path short from the VIN pin through the input bypass
CSS (Pin 5/Pin 9):
A capacitor from the CSS pin to the capacitor, through the catch diode back to SW. All trace regulated output voltage determines the output voltage inductance on this path will create a voltage spike at switch ramp rate during start-up. When the current through the off, adding to the VCE voltage across the internal NPN. CSS capacitor exceeds the CSS threshold (ICSS), the volt- age ramp of the output is limited. The CSS threshold is
BOOST (Pin 3/Pin 6):
The BOOST pin is used to provide a proportional to the FB voltage (see Typical Performance drive voltage, higher than the input voltage, to the internal Characteristics) and is defeated for FB voltage greater than bipolar NPN power switch. Without this added voltage, the 0.9V (typical). See Soft-Start section in Applications Infor- typical switch voltage loss would be about 1.5V. The mation for details. additional BOOST voltage allows the switch to saturate 3437fc 8
