Datasheet LT3434 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | High Voltage 3A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current |
| Pages / Page | 24 / 7 — PI FU CTIO S. FB (Pin 12):. GND (Pins 8, 17):. PGFB (PIN 13):. CSS (Pin … |
| File Format / Size | PDF / 418 Kb |
| Document Language | English |
PI FU CTIO S. FB (Pin 12):. GND (Pins 8, 17):. PGFB (PIN 13):. CSS (Pin 9):. SYNC (Pin 14):. SHDN (Pin 15):. BIAS (Pin 10):
Model Line for this Datasheet
Text Version of Document
LT3434
U U U PI FU CTIO S
from the CT pin into the external capacitor. When the volt- serve as a current clamp or control loop override. VC sits age on the external capacitor reaches an internal clamp at about 0.65V for light loads and 2.2V at maximum load. (VCT), the PG pin becomes a high impedance node. The During the sleep portion of Burst Mode operation, the VC resultant PG delay time is given by t = CCT • VCT/ICT. If the pin is held at a voltage slightly below the burst threshold voltage on the PGFB pin drops below VPGFB, CCT will be for better transient response. Driving the VC pin to ground discharged rapidly to 0V and PG will be active low with a will disable switching and place the IC into sleep mode. 200µA sink capability. If the CT pin is clamped (Power Good
FB (Pin 12):
The feedback pin is used to determine the condition) during normal operation and SHDN is taken low, output voltage using an external voltage divider from the the CT pin will be discharged and a delay period will occur output that generates 1.25V at the FB pin . When the FB pin when SHDN is returned high. See the Power Good section drops below 0.9V, switching frequency is reduced, the in Applications Information for details. SYNC function is disabled and output ramp rate control is
GND (Pins 8, 17):
The GND pin connection acts as the enabled via the CSS pin. See the Feedback section in reference for the regulated output, so load regulation will Applications Information for details. suffer if the “ground” end of the load is not at the same
PGFB (PIN 13):
The PGFB pin is the positive input to a voltage as the GND pin of the IC. This condition will occur comparator whose negative input is set at VPGFB. When when load current or other currents flow through metal PGFB is taken above VPGFB, current (ICSS) is sourced into paths between the GND pin and the load ground. Keep the the CT pin starting the PG delay period. When the voltage path between the GND pin and the load ground short and on the PGFB pin drops below VPGFB, the CT pin is rapidly use a ground plane when possible. The GND pin also acts discharged resetting the PG delay period. The PGFB volt- as a heat sink and should be soldered (along with the age is typically generated by a resistive divider from the exposed leadframe) to the copper ground plane to reduce regulated output or input supply. See Power Good section thermal resistance (see Applications Information). in Applications Information for details.
CSS (Pin 9):
A capacitor from the CSS pin to the regulated
SYNC (Pin 14):
The SYNC pin is used to synchronize the output voltage determines the output voltage ramp rate internal oscillator to an external signal. It is directly logic during start-up. When the current through the CSS capaci- compatible and can be driven with any signal between tor exceeds the CSS threshold (ICSS), the voltage ramp of 30% and 70% duty cycle. The synchronizing range is the output is limited. The CSS threshold is proportional to equal to maximum initial operating frequency up to 700kHz. the FB voltage (see Typical Performance Characteristics) When the voltage on the FB pin is below 0.9V the SYNC and is defeated for FB voltage greater than 0.9V (typical). function is disabled. See the Synchronizing section in See Soft-Start section in Applications Information for Applications Information for details. details.
SHDN (Pin 15):
The SHDN pin is used to turn off the
BIAS (Pin 10):
The BIAS pin is used to improve efficiency regulator and to reduce input current to less than 1µA. The when operating at higher input voltages and light load SHDN pin requires a voltage above 1.3V with a typical current. Connecting this pin to the regulated output volt- source current of 5µA to take the IC out of the shutdown age forces most of the internal circuitry to draw its state. operating current from the output voltage rather than the input supply. This architecture increases efficiency espe-
PG (Pin 16):
The PG pin is functional only when the SHDN cially when the input voltage is much higher than the pin is above its threshold, and is active low when the output. Minimum output voltage setting for this mode of internal clamp on the CT pin is below its clamp level and operation is 3V. high impedance when the clamp is active. The PG pin has a typical sink capability of 200µA. See the Power Good
VC (Pin 11):
The VC pin is the output of the error amplifier section in Applications Information for details. and the input of the peak switch current comparator. It is normally used for frequency compensation, but can also 3434fb 7
U U U PI FU CTIO S
from the CT pin into the external capacitor. When the volt- serve as a current clamp or control loop override. VC sits age on the external capacitor reaches an internal clamp at about 0.65V for light loads and 2.2V at maximum load. (VCT), the PG pin becomes a high impedance node. The During the sleep portion of Burst Mode operation, the VC resultant PG delay time is given by t = CCT • VCT/ICT. If the pin is held at a voltage slightly below the burst threshold voltage on the PGFB pin drops below VPGFB, CCT will be for better transient response. Driving the VC pin to ground discharged rapidly to 0V and PG will be active low with a will disable switching and place the IC into sleep mode. 200µA sink capability. If the CT pin is clamped (Power Good
FB (Pin 12):
The feedback pin is used to determine the condition) during normal operation and SHDN is taken low, output voltage using an external voltage divider from the the CT pin will be discharged and a delay period will occur output that generates 1.25V at the FB pin . When the FB pin when SHDN is returned high. See the Power Good section drops below 0.9V, switching frequency is reduced, the in Applications Information for details. SYNC function is disabled and output ramp rate control is
GND (Pins 8, 17):
The GND pin connection acts as the enabled via the CSS pin. See the Feedback section in reference for the regulated output, so load regulation will Applications Information for details. suffer if the “ground” end of the load is not at the same
PGFB (PIN 13):
The PGFB pin is the positive input to a voltage as the GND pin of the IC. This condition will occur comparator whose negative input is set at VPGFB. When when load current or other currents flow through metal PGFB is taken above VPGFB, current (ICSS) is sourced into paths between the GND pin and the load ground. Keep the the CT pin starting the PG delay period. When the voltage path between the GND pin and the load ground short and on the PGFB pin drops below VPGFB, the CT pin is rapidly use a ground plane when possible. The GND pin also acts discharged resetting the PG delay period. The PGFB volt- as a heat sink and should be soldered (along with the age is typically generated by a resistive divider from the exposed leadframe) to the copper ground plane to reduce regulated output or input supply. See Power Good section thermal resistance (see Applications Information). in Applications Information for details.
CSS (Pin 9):
A capacitor from the CSS pin to the regulated
SYNC (Pin 14):
The SYNC pin is used to synchronize the output voltage determines the output voltage ramp rate internal oscillator to an external signal. It is directly logic during start-up. When the current through the CSS capaci- compatible and can be driven with any signal between tor exceeds the CSS threshold (ICSS), the voltage ramp of 30% and 70% duty cycle. The synchronizing range is the output is limited. The CSS threshold is proportional to equal to maximum initial operating frequency up to 700kHz. the FB voltage (see Typical Performance Characteristics) When the voltage on the FB pin is below 0.9V the SYNC and is defeated for FB voltage greater than 0.9V (typical). function is disabled. See the Synchronizing section in See Soft-Start section in Applications Information for Applications Information for details. details.
SHDN (Pin 15):
The SHDN pin is used to turn off the
BIAS (Pin 10):
The BIAS pin is used to improve efficiency regulator and to reduce input current to less than 1µA. The when operating at higher input voltages and light load SHDN pin requires a voltage above 1.3V with a typical current. Connecting this pin to the regulated output volt- source current of 5µA to take the IC out of the shutdown age forces most of the internal circuitry to draw its state. operating current from the output voltage rather than the input supply. This architecture increases efficiency espe-
PG (Pin 16):
The PG pin is functional only when the SHDN cially when the input voltage is much higher than the pin is above its threshold, and is active low when the output. Minimum output voltage setting for this mode of internal clamp on the CT pin is below its clamp level and operation is 3V. high impedance when the clamp is active. The PG pin has a typical sink capability of 200µA. See the Power Good
VC (Pin 11):
The VC pin is the output of the error amplifier section in Applications Information for details. and the input of the peak switch current comparator. It is normally used for frequency compensation, but can also 3434fb 7
