Datasheet LT3800 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | High-Voltage Synchronous Current Mode Step-Down Controller |
| Pages / Page | 24 / 6 — PIN FUNCTIONS. SENSE– (Pin 8):. SENSE+ (Pin 9):. PGND (Pin 10):. FB (Pin … |
| File Format / Size | PDF / 265 Kb |
| Document Language | English |
PIN FUNCTIONS. SENSE– (Pin 8):. SENSE+ (Pin 9):. PGND (Pin 10):. FB (Pin 6):. BG (Pin 11):. CC (Pin 12):. NC (Pin 13):. SW (Pin 14):
Model Line for this Datasheet
Text Version of Document
LT3800
PIN FUNCTIONS
and reverse-current inhibit functions are enabled. When VC pin is set at 100mV below the burst threshold, which the pin voltage is above 0.5V, Burst Mode operation is dis- limits the negative excursion of the pin voltage. There- abled, but reverse-current inhibit operation is maintained. fore, this pin cannot be pulled low with a low-impedance DC/DC converters operating with reverse-current inhibit source. If the VC pin must be externally manipulated, do operation (BURST_EN = VFB) have a 1mA minimum load so through a 1kΩ series resistance. requirement. Reverse-current inhibit is disabled when the
SENSE– (Pin 8):
Negative Input for Current Sense Ampli- pin voltage is above 2.5V. This pin is typically shorted to fi er. Sensed inductor current limit set at ±150mV across ground to enable Burst Mode operation and reverse-current SENSE inputs. inhibit, shorted to VFB to disable Burst Mode operation while enabling reverse-current inhibit, and connected
SENSE+ (Pin 9):
Positive Input for Current Sense Ampli- to V fi er. Sensed inductor current limit set at ±150mV across CC pin to disable both functions. See Applications Information section. SENSE inputs.
V PGND (Pin 10):
High Current Ground Reference for Syn-
FB (Pin 6):
Error Amplifi er Inverting Input. The noninvert- ing input of the error amplifi er is connected to an internal chronous Switch. Current path from pin to negative terminal 1.231V reference. Desired converter output voltage (V of V OUT) CC decoupling capacitor must not corrupt SGND. is programmed by connecting a resistive divider from the
BG (Pin 11):
Synchronous Switch Gate Drive Output. converter output to the VFB pin. Values for the resistor connected from V
V
OUT to VFB (R2) and the resistor con-
CC (Pin 12):
Internal Regulator Output. Most IC func- nected from V tions are powered from this pin. Driving this pin from FB to ground (R1) can be calculated via the following relationship: an external source reduces VIN pin current to 20μA. This pin is decoupled with a low ESR 1μF capacitor to V PGND. In shutdown mode, this pin sinks 20μA until the R2 = R1• OUT – 1 pin voltage is discharged to 0V. See Typical Performance 1.231 Characteristics. The VFB pin input bias current is 25nA, so use of extremely
NC (Pin 13):
No Connection. high value feedback resistors could cause a converter output that is slightly higher than expected. Bias current
SW (Pin 14):
Reference for VBOOST Supply and High Cur- error at the output can be estimated as: rent Return for Bootstrapped Switch. ∆VOUT(BIAS) = 25nA • R2
TG (Pin 15):
Bootstrapped Switch Gate Drive Output.
VC (Pin 7):
Error Amplifi er Output. The voltage on the VC
BOOST (Pin 16):
Bootstrapped Supply – Maximum Operat- pin corresponds to the maximum (peak) switch current per ing Voltage (Ground Referred) to 75V. This pin is decoupled oscillator cycle. The error amplifi er is typically confi gured with a low ESR 1μF capacitor to pin SW. The voltage on as an integrator by connecting an RC network from this the decoupling capacitor is refreshed through a rectifi er pin to ground. This network creates the dominant pole for from either VCC or an external source. the converter voltage regulation feedback loop. Specifi c
Exposed Package Backside (SGND) (Pin 17):
Low Noise integrator characteristics can be confi gured to optimize Ground Reference. SGND connection is made through transient response. Connecting a 100pF or greater high the exposed lead frame on back of TSSOP package which frequency bypass capacitor from this pin to ground is also must be soldered to the PCB ground. recommended. When Burst Mode operation is enabled (see Pin 5 description), an internal low impedance clamp on the 3800fc 6 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
PIN FUNCTIONS
and reverse-current inhibit functions are enabled. When VC pin is set at 100mV below the burst threshold, which the pin voltage is above 0.5V, Burst Mode operation is dis- limits the negative excursion of the pin voltage. There- abled, but reverse-current inhibit operation is maintained. fore, this pin cannot be pulled low with a low-impedance DC/DC converters operating with reverse-current inhibit source. If the VC pin must be externally manipulated, do operation (BURST_EN = VFB) have a 1mA minimum load so through a 1kΩ series resistance. requirement. Reverse-current inhibit is disabled when the
SENSE– (Pin 8):
Negative Input for Current Sense Ampli- pin voltage is above 2.5V. This pin is typically shorted to fi er. Sensed inductor current limit set at ±150mV across ground to enable Burst Mode operation and reverse-current SENSE inputs. inhibit, shorted to VFB to disable Burst Mode operation while enabling reverse-current inhibit, and connected
SENSE+ (Pin 9):
Positive Input for Current Sense Ampli- to V fi er. Sensed inductor current limit set at ±150mV across CC pin to disable both functions. See Applications Information section. SENSE inputs.
V PGND (Pin 10):
High Current Ground Reference for Syn-
FB (Pin 6):
Error Amplifi er Inverting Input. The noninvert- ing input of the error amplifi er is connected to an internal chronous Switch. Current path from pin to negative terminal 1.231V reference. Desired converter output voltage (V of V OUT) CC decoupling capacitor must not corrupt SGND. is programmed by connecting a resistive divider from the
BG (Pin 11):
Synchronous Switch Gate Drive Output. converter output to the VFB pin. Values for the resistor connected from V
V
OUT to VFB (R2) and the resistor con-
CC (Pin 12):
Internal Regulator Output. Most IC func- nected from V tions are powered from this pin. Driving this pin from FB to ground (R1) can be calculated via the following relationship: an external source reduces VIN pin current to 20μA. This pin is decoupled with a low ESR 1μF capacitor to V PGND. In shutdown mode, this pin sinks 20μA until the R2 = R1• OUT – 1 pin voltage is discharged to 0V. See Typical Performance 1.231 Characteristics. The VFB pin input bias current is 25nA, so use of extremely
NC (Pin 13):
No Connection. high value feedback resistors could cause a converter output that is slightly higher than expected. Bias current
SW (Pin 14):
Reference for VBOOST Supply and High Cur- error at the output can be estimated as: rent Return for Bootstrapped Switch. ∆VOUT(BIAS) = 25nA • R2
TG (Pin 15):
Bootstrapped Switch Gate Drive Output.
VC (Pin 7):
Error Amplifi er Output. The voltage on the VC
BOOST (Pin 16):
Bootstrapped Supply – Maximum Operat- pin corresponds to the maximum (peak) switch current per ing Voltage (Ground Referred) to 75V. This pin is decoupled oscillator cycle. The error amplifi er is typically confi gured with a low ESR 1μF capacitor to pin SW. The voltage on as an integrator by connecting an RC network from this the decoupling capacitor is refreshed through a rectifi er pin to ground. This network creates the dominant pole for from either VCC or an external source. the converter voltage regulation feedback loop. Specifi c
Exposed Package Backside (SGND) (Pin 17):
Low Noise integrator characteristics can be confi gured to optimize Ground Reference. SGND connection is made through transient response. Connecting a 100pF or greater high the exposed lead frame on back of TSSOP package which frequency bypass capacitor from this pin to ground is also must be soldered to the PCB ground. recommended. When Burst Mode operation is enabled (see Pin 5 description), an internal low impedance clamp on the 3800fc 6 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
