Datasheet LT1776 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Wide Input Range, High Efficiency, Step-Down Switching Regulator |
| Pages / Page | 20 / 7 — TIMING DIAGRAMS. High dV/dt Mode. Low dV/dt Mode. OPERATIO. Output Switch … |
| File Format / Size | PDF / 235 Kb |
| Document Language | English |
TIMING DIAGRAMS. High dV/dt Mode. Low dV/dt Mode. OPERATIO. Output Switch Theory
Model Line for this Datasheet
Text Version of Document
LT1776
W U W TIMING DIAGRAMS High dV/dt Mode Low dV/dt Mode
V V IN IN V V SW SW 0 0 SWDR SWDR SWON SWON BOOST BOOST SWOFF SWOFF 1776 TD01 1776 TD02
U OPERATIO
The LT1776 is a current mode switching regulator IC that Fast positive-going slew rate action is provided by lateral has been optimized for high efficiency operation in high PNP Q3 driving the Darlington arrangement of Q1 and Q2. input voltage, low output voltage buck topologies. The The extra β available from Q2 greatly reduces the drive Block Diagram shows an overall view of the system. requirements of Q3. Several of the blocks are straightforward and similar to Although desirable for dynamic reasons, this topology those found in traditional designs, including: Internal Bias alone will yield a large DC forward voltage drop. A second Regulator, Oscillator and Feedback Amplifier. The novel lateral PNP, Q4, acts directly on the base of Q1 to reduce portion includes an elaborate Output Switch section and the voltage drop after the slewing phase has taken place. Logic Section to provide the control signals required by To achieve the desired high slew rate, PNPs Q3 and Q4 are the switch section. “force-fed” packets of charge via the current sources The LT1776 operates much the same as traditional controlled by the boost signal. current mode switchers, the major difference being its Please refer to the High dV/dt Mode Timing Diagram. A specialized output switch section. Due to space con- typical oscillator cycle is as follows: The logic section first straints, this discussion will not reiterate the basics of generates an SWDR signal that powers up the current current mode switcher/controllers and the “buck” topol- comparator and allows it time to settle. About 1µs later, the ogy. A good source of information on these topics is SWON signal is asserted and the BOOST signal is pulsed Application Note 19. for a few hundred nanoseconds. After a short delay, the V
Output Switch Theory
SW pin slews rapidly to VIN. Later, after the peak switch current indicated by the control voltage VC has been One of the classic problems in delivering low output reached (current mode control), the SWON and SWDR voltage from high input voltage at good efficiency is that signals are turned off, and SWOFF is pulsed for several minimizing AC switching losses requires very fast volt- hundred nanoseconds. The use of an explicit turn-off age (dV/dt) and current (dI/dt) transition at the output device, i.e., Q5, improves turn-off response time and thus device. This is in spite of the fact that in a bipolar aids both controllability and efficiency. implementation, slow lateral PNPs must be included in the switching signal path. 7
W U W TIMING DIAGRAMS High dV/dt Mode Low dV/dt Mode
V V IN IN V V SW SW 0 0 SWDR SWDR SWON SWON BOOST BOOST SWOFF SWOFF 1776 TD01 1776 TD02
U OPERATIO
The LT1776 is a current mode switching regulator IC that Fast positive-going slew rate action is provided by lateral has been optimized for high efficiency operation in high PNP Q3 driving the Darlington arrangement of Q1 and Q2. input voltage, low output voltage buck topologies. The The extra β available from Q2 greatly reduces the drive Block Diagram shows an overall view of the system. requirements of Q3. Several of the blocks are straightforward and similar to Although desirable for dynamic reasons, this topology those found in traditional designs, including: Internal Bias alone will yield a large DC forward voltage drop. A second Regulator, Oscillator and Feedback Amplifier. The novel lateral PNP, Q4, acts directly on the base of Q1 to reduce portion includes an elaborate Output Switch section and the voltage drop after the slewing phase has taken place. Logic Section to provide the control signals required by To achieve the desired high slew rate, PNPs Q3 and Q4 are the switch section. “force-fed” packets of charge via the current sources The LT1776 operates much the same as traditional controlled by the boost signal. current mode switchers, the major difference being its Please refer to the High dV/dt Mode Timing Diagram. A specialized output switch section. Due to space con- typical oscillator cycle is as follows: The logic section first straints, this discussion will not reiterate the basics of generates an SWDR signal that powers up the current current mode switcher/controllers and the “buck” topol- comparator and allows it time to settle. About 1µs later, the ogy. A good source of information on these topics is SWON signal is asserted and the BOOST signal is pulsed Application Note 19. for a few hundred nanoseconds. After a short delay, the V
Output Switch Theory
SW pin slews rapidly to VIN. Later, after the peak switch current indicated by the control voltage VC has been One of the classic problems in delivering low output reached (current mode control), the SWON and SWDR voltage from high input voltage at good efficiency is that signals are turned off, and SWOFF is pulsed for several minimizing AC switching losses requires very fast volt- hundred nanoseconds. The use of an explicit turn-off age (dV/dt) and current (dI/dt) transition at the output device, i.e., Q5, improves turn-off response time and thus device. This is in spite of the fact that in a bipolar aids both controllability and efficiency. implementation, slow lateral PNPs must be included in the switching signal path. 7
