Datasheet LTC6401-20 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 1.3GHz Low Noise, Low Distortion Differential ADC Driver for 140MHz IF |
| Pages / Page | 16 / 9 — PIN FUNCTIONS. V+ (Pins 1, 3, 10):. –OUTF, +OUTF (Pins 6, 7):. E (Pin … |
| File Format / Size | PDF / 230 Kb |
| Document Language | English |
PIN FUNCTIONS. V+ (Pins 1, 3, 10):. –OUTF, +OUTF (Pins 6, 7):. E (Pin 11):. VOCM (Pin 2):. +IN (Pins 13, 14):
Model Line for this Datasheet
Text Version of Document
LTC6401-20
PIN FUNCTIONS V+ (Pins 1, 3, 10):
Positive Power Supply (Normally tied
–OUTF, +OUTF (Pins 6, 7):
Filtered Outputs. These pins have to 3V or 3.3V). All three pins must be tied to the same 50Ω series resistors and a 1.7pF shunt capacitance. voltage. Bypass each pin with 1000pF and 0.1μF capaci- ⎯
E
⎯
N
⎯
A
⎯
B
⎯
L
⎯
E (Pin 11):
This pin is a logic input referenced to tors as close to the pins as possible. V–. If low, the part is enabled. If high, the part is disabled
VOCM (Pin 2):
This pin sets the output common mode and draws approximately 1mA supply current. voltage. A 0.1μF external bypass capacitor is recom-
+IN (Pins 13, 14):
Positive Input. Pins 13 and 14 are mended. internally shorted together.
V– (Pins 4, 9, 12, 17):
Negative Power Supply. All four
–IN (Pins 15, 16):
Negative Input. Pins 15 and 16 are pins must be connected to the same voltage/ground. internally shorted together.
–OUT, +OUT (Pins 5, 8):
Unfi ltered Outputs. These pins
Exposed Pad (Pin 17):
V–. The Exposed Pad must be con- have 12.5Ω series resistors. nected to the same voltage/ground as pins 4, 9, 12.
BLOCK DIAGRAM
V– ENABLE V+ V– 12 11 10 9 BIAS CONTROL RG RF ROUT +IN +OUT 100Ω 1000Ω 12.5Ω 13 8 RFILT +OUTF 50Ω +IN IN+ OUT– 7 14 C R FILT FILT –IN 1.7pF –OUTF 50Ω 15 6 IN– OUT+ RG RF ROUT –IN –OUT 100Ω 1000Ω 12.5Ω 16 5 2k COMMON MODE CONTROL 5.3pF 640120 BD 1 2 3 4 V+ VOCM V+ V– 640120f 9
PIN FUNCTIONS V+ (Pins 1, 3, 10):
Positive Power Supply (Normally tied
–OUTF, +OUTF (Pins 6, 7):
Filtered Outputs. These pins have to 3V or 3.3V). All three pins must be tied to the same 50Ω series resistors and a 1.7pF shunt capacitance. voltage. Bypass each pin with 1000pF and 0.1μF capaci- ⎯
E
⎯
N
⎯
A
⎯
B
⎯
L
⎯
E (Pin 11):
This pin is a logic input referenced to tors as close to the pins as possible. V–. If low, the part is enabled. If high, the part is disabled
VOCM (Pin 2):
This pin sets the output common mode and draws approximately 1mA supply current. voltage. A 0.1μF external bypass capacitor is recom-
+IN (Pins 13, 14):
Positive Input. Pins 13 and 14 are mended. internally shorted together.
V– (Pins 4, 9, 12, 17):
Negative Power Supply. All four
–IN (Pins 15, 16):
Negative Input. Pins 15 and 16 are pins must be connected to the same voltage/ground. internally shorted together.
–OUT, +OUT (Pins 5, 8):
Unfi ltered Outputs. These pins
Exposed Pad (Pin 17):
V–. The Exposed Pad must be con- have 12.5Ω series resistors. nected to the same voltage/ground as pins 4, 9, 12.
BLOCK DIAGRAM
V– ENABLE V+ V– 12 11 10 9 BIAS CONTROL RG RF ROUT +IN +OUT 100Ω 1000Ω 12.5Ω 13 8 RFILT +OUTF 50Ω +IN IN+ OUT– 7 14 C R FILT FILT –IN 1.7pF –OUTF 50Ω 15 6 IN– OUT+ RG RF ROUT –IN –OUT 100Ω 1000Ω 12.5Ω 16 5 2k COMMON MODE CONTROL 5.3pF 640120 BD 1 2 3 4 V+ VOCM V+ V– 640120f 9
