Datasheet LT1920 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Single Resistor Gain Programmable, Precision Instrumentation Amplifier |
| Pages / Page | 12 / 8 — BLOCK DIAGRAM. Figure 1. Block Diagram. THEORY OF OPERATIO |
| File Format / Size | PDF / 308 Kb |
| Document Language | English |
BLOCK DIAGRAM. Figure 1. Block Diagram. THEORY OF OPERATIO
Model Line for this Datasheet
Text Version of Document
LT1920
W BLOCK DIAGRAM
VB V + + R5 R6 10k 10k A1 6 OUTPUT – R3 C1 400Ω –IN 2 Q1 R1 – 24.7k V – A3 + RG 1 R V – G 8 VB V + R7 R8 + 10k 10k A2 5 REF – R4 C2 400Ω +IN 3 Q2 V – R2 24.7k 7 V + V – 4 V – PREAMP STAGE DIFFERENCE AMPLIFIER STAGE 1920 F01
Figure 1. Block Diagram U THEORY OF OPERATIO
The LT1920 is a modified version of the three op amp with programmed gain. Therefore, the bandwidth does not instrumentation amplifier. Laser trimming and monolithic drop proportional to gain. construction allow tight matching and tracking of circuit The input transistors Q1 and Q2 offer excellent matching, parameters over the specified temperature range. Refer to which is inherent in NPN bipolar transistors, as well as the block diagram (Figure 1) to understand the following picoampere input bias current due to superbeta process- circuit description. The collector currents in Q1 and Q2 are ing. The collector currents in Q1 and Q2 are held constant trimmed to minimize offset voltage drift, thus assuring a due to the feedback through the Q1-A1-R1 loop and high level of performance. R1 and R2 are trimmed to an Q2-A2-R2 loop which in turn impresses the differential absolute value of 24.7k to assure that the gain can be set input voltage across the external gain set resistor RG. accurately (0.3% at G = 100) with only one external Since the current that flows through RG also flows through resistor RG. The value of RG in parallel with R1 (R2) R1 and R2, the ratios provide a gained-up differential volt- determines the transconductance of the preamp stage. As age, G = (R1 + R2)/RG, to the unity-gain difference amplifier RG is reduced for larger programmed gains, the transcon- A3. The common mode voltage is removed by A3, result- ductance of the input preamp stage increases to that of the ing in a single-ended output voltage referenced to the input transistors Q1 and Q2. This increases the open-loop voltage on the REF pin. The resulting gain equation is: gain when the programmed gain is increased, reducing the input referred gain related errors and noise. The input V + – OUT – VREF = G(VIN – VIN ) voltage noise at gains greater than 50 is determined only where: by Q1 and Q2. At lower gains the noise of the difference G = (49.4kΩ / RG) + 1 amplifier and preamp gain setting resistors increase the solving for the gain set resistor gives: noise. The gain bandwidth product is determined by C1, C2 and the preamp transconductance which increases RG = 49.4kΩ/(G – 1) 8
W BLOCK DIAGRAM
VB V + + R5 R6 10k 10k A1 6 OUTPUT – R3 C1 400Ω –IN 2 Q1 R1 – 24.7k V – A3 + RG 1 R V – G 8 VB V + R7 R8 + 10k 10k A2 5 REF – R4 C2 400Ω +IN 3 Q2 V – R2 24.7k 7 V + V – 4 V – PREAMP STAGE DIFFERENCE AMPLIFIER STAGE 1920 F01
Figure 1. Block Diagram U THEORY OF OPERATIO
The LT1920 is a modified version of the three op amp with programmed gain. Therefore, the bandwidth does not instrumentation amplifier. Laser trimming and monolithic drop proportional to gain. construction allow tight matching and tracking of circuit The input transistors Q1 and Q2 offer excellent matching, parameters over the specified temperature range. Refer to which is inherent in NPN bipolar transistors, as well as the block diagram (Figure 1) to understand the following picoampere input bias current due to superbeta process- circuit description. The collector currents in Q1 and Q2 are ing. The collector currents in Q1 and Q2 are held constant trimmed to minimize offset voltage drift, thus assuring a due to the feedback through the Q1-A1-R1 loop and high level of performance. R1 and R2 are trimmed to an Q2-A2-R2 loop which in turn impresses the differential absolute value of 24.7k to assure that the gain can be set input voltage across the external gain set resistor RG. accurately (0.3% at G = 100) with only one external Since the current that flows through RG also flows through resistor RG. The value of RG in parallel with R1 (R2) R1 and R2, the ratios provide a gained-up differential volt- determines the transconductance of the preamp stage. As age, G = (R1 + R2)/RG, to the unity-gain difference amplifier RG is reduced for larger programmed gains, the transcon- A3. The common mode voltage is removed by A3, result- ductance of the input preamp stage increases to that of the ing in a single-ended output voltage referenced to the input transistors Q1 and Q2. This increases the open-loop voltage on the REF pin. The resulting gain equation is: gain when the programmed gain is increased, reducing the input referred gain related errors and noise. The input V + – OUT – VREF = G(VIN – VIN ) voltage noise at gains greater than 50 is determined only where: by Q1 and Q2. At lower gains the noise of the difference G = (49.4kΩ / RG) + 1 amplifier and preamp gain setting resistors increase the solving for the gain set resistor gives: noise. The gain bandwidth product is determined by C1, C2 and the preamp transconductance which increases RG = 49.4kΩ/(G – 1) 8
