Datasheet LT1818, LT1819 (Analog Devices) - 10

LT1818/LT1819
APPLICATIONS INFORMATION Layout and Passive Components
load, a resistor of 10Ω to 50Ω must be connected between the output and the capacitive load to avoid ringing or As with all high speed amplifi ers, the LT1818/LT1819 oscillation (see R require some attention to board layout. A ground plane S in Figure 1). The feedback must still be taken directly from the output so that the series resistor is recommended and trace lengths should be minimized, will isolate the capacitive load to ensure stability. especially on the negative input lead. Low ESL/ESR bypass capacitors should be placed directly
Input Considerations
at the positive and negative supply (0.01μF ceramics are The inputs of the LT1818/LT1819 amplifi ers are connected recommended). For high drive current applications, ad- to the bases of NPN and PNP bipolar transistors in paral- ditional 1μF to 10μF tantalums should be added. lel. The base currents are of opposite polarity and provide The parallel combination of the feedback resistor and gain fi rst order bias current cancellation. Due to variation in the setting resistor on the inverting input combine with the matching of NPN and PNP beta, the polarity of the input input capacitance to form a pole that can cause peaking or bias current can be positive or negative. The offset current, even oscillations. If feedback resistors greater than 500Ω however, does not depend on beta matching and is tightly are used, a parallel capacitor of value controlled. Therefore, the use of balanced source resistance at each input is recommended for applications where DC CF > RG • CIN/RF accuracy must be maximized. For example, with a 100Ω should be used to cancel the input pole and optimize source resistance at each input, the 800nA maximum offset dynamic performance (see Figure 1). For applications current results in only 80μV of extra offset, while without where the DC noise gain is 1 and a large feedback resis- balance the 8μA maximum input bias current could result tor is used, CF should be greater than or equal to CIN. An in an 0.8mV offset condition. example would be an I-to-V converter. The inputs can withstand differential input voltages of In high closed-loop gain confi gurations, RF >> RG, no CF up to 6V without damage and without needing clamping needs to be added. To optimize the bandwidth in these or series resistance for protection. This differential input applications, a capacitor, CG, may be added in parallel with voltage generates a large internal current (up to 50mA), RG in order to cancel out any parasitic CF capacitance. which results in the high slew rate. In normal transient closed-loop operation, this does not increase power dis-
Capacitive Loading
sipation signifi cantly because of the low duty cycle of the The LT1818/LT1819 are optimized for low distortion and transient inputs. Sustained differential inputs, however, high gain bandwidth applications. The amplifi ers can drive will result in excessive power dissipation and therefore a capacitive load of 20pF in a unity-gain confi guration and
this device should not be used as a comparator.
more with higher gain. When driving a larger capacitive IN+ + RS RG IN– – CLOAD CG RF CF 18189 F01
Figure 1
18189fb 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION E LECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION TYPICAL APPLICATION SIMPLIFIED SCHEMATIC PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS