Datasheet LTC3815 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 6A Monolithic Synchronous DC/DC Step-Down Converter with Digital Power System Management |
| Pages / Page | 42 / 10 — PIN FUNCTIONS RT (Pin 1):. SW (Pins 10, 11, 13, 14, 18, 19, 21, 22, 23):. … |
| Revision | B |
| File Format / Size | PDF / 3.0 Mb |
| Document Language | English |
PIN FUNCTIONS RT (Pin 1):. SW (Pins 10, 11, 13, 14, 18, 19, 21, 22, 23):. NC (Pins 12, 20):. ASEL (Pin 2):. IN (Pins 15-17):
Model Line for this Datasheet
Text Version of Document
link to page 34 LTC3815
PIN FUNCTIONS RT (Pin 1):
Oscillator Frequency. This pin provides two
SW (Pins 10, 11, 13, 14, 18, 19, 21, 22, 23):
Switching modes of setting the constant switching frequency. Node. This pin connects to the drains of the internal main Connect a resistor from RT pin to ground to program the and synchronous power MOSFET switches. switching frequency from 400kHz to 3MHz. Tying this
NC (Pins 12, 20):
No Connection. Can be connected to pin to VIN enables the internal 1MHz oscillator frequency. ground or left open. This pin does not connect to any
ASEL (Pin 2):
Serial Bus Address Configuration Input. internal circuitry. Connect a ±1% resistor from this pin to ground in order
PV
to select the 3 LSBs of the serial bus interface address.
IN (Pins 15-17):
Power Input Supply. PVIN connects to the source of the internal P-channel power MOSFET. This (see Table 7). pin is independent of VIN and may be connected to the
MARGIN (Pin 3):
Fast Margining Select. In the default same voltage or to a
lower
voltage supply. mode when this pin is floating, the reference voltage
PGOOD (Pin 29):
Power Good. This open-drain output margin offset is changed with MFR_VOUT_COMMAND is pulled down to SGND on start-up and while the out- through the serial interface. If this pin is pulled high, the put voltage is outside the power good window set by reference voltage margin offset is immediately ramped to the PGLIM pin. If the output voltage increases and stays the value pre-stored in the MFR_VOUT_MARGIN_HIGH inside the power good window for more than the delay register. If this pin is pulled low, the reference voltage mar- programmed at the PGFD pin, the PGOOD pin is released. gin offset is immediately ramped to the value pre-stored If the output voltage leaves the power good window for in MFR_VOUT_MARGIN_LOW register. more than 16 switching cycles the PGOOD pin is pulled
WP (Pin 4):
Write Protect Pin. Pulling this pin high dis- down. ables writes to MFR_VOUT_COMMAND, MFR_VOUT_
V
MARGIN_HIGH, and MFR_VOUT_MARGIN_LOW. When
IN (Pin 24):
Signal Input Supply. Decouple this pin to SGND with a capacitor. This pin powers the internal con- this pin is grounded, there are no write restrictions. trol circuitry. This pin is independent of PVIN and may
ALERT (Pin 5):
Open Drain Digital Output. Connect the be connected to the same voltage or to a
higher
supply system SMBALERT interrupt signal to this pin. A pull-up voltage. resistor is required in the application.
PGFD (Pin 25):
PGOOD Deglitch Filter Delay Select. The
CLKOUT (Pin 6):
Clock Out Signal for 2-Phase Operation. voltage at this pin sets the delay that the output must be The phase of this clock is 180° with respect to the internal in regulation before the PGOOD flag is asserted. The delay clock. Signal swing is from VIN to GND. can be programmed to one of seven discrete values where
SDA (Pin 7):
Serial Bus Data Input and Output. A pull-up tDELAY = 200μs • 2N (N = 0 to 5, 7). resistor is required in the application.
RUN_MSTR (Pin 26):
Master Run. The power up thresh-
SCL (Pin 8):
Serial Bus Clock Input. A pull-up resistor is old is set at 1V. When forced below 0.4V, all circuitry is required in the application. shut off and the IC is put into a low current shutdown mode (IQ < 1μA).
MODE/SYNC (Pin 9):
Mode Selection and External Clock Input. If this pin is tied to V
RUN_STBY (Pin 27):
Standby Mode Off. The regulator IN, discontinuous mode is enabled at light loads. If this pin is connected to ground, power up threshold is set at 1V. When forced below 0.4V, forced continuous mode is selected. Driving the MODE/ only the voltage regulator is shut off while the ADC and SYNC pin with an external clock signal will synchronize PMBus interface are still active. When shut off, the ADC the switching frequency to the applied frequency. There refresh rate is reduced to 1Hz and the IC quiescent current is an internal 20k resistor to ground on this pin. Rev B 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information PMBus Command Details Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS RT (Pin 1):
Oscillator Frequency. This pin provides two
SW (Pins 10, 11, 13, 14, 18, 19, 21, 22, 23):
Switching modes of setting the constant switching frequency. Node. This pin connects to the drains of the internal main Connect a resistor from RT pin to ground to program the and synchronous power MOSFET switches. switching frequency from 400kHz to 3MHz. Tying this
NC (Pins 12, 20):
No Connection. Can be connected to pin to VIN enables the internal 1MHz oscillator frequency. ground or left open. This pin does not connect to any
ASEL (Pin 2):
Serial Bus Address Configuration Input. internal circuitry. Connect a ±1% resistor from this pin to ground in order
PV
to select the 3 LSBs of the serial bus interface address.
IN (Pins 15-17):
Power Input Supply. PVIN connects to the source of the internal P-channel power MOSFET. This (see Table 7). pin is independent of VIN and may be connected to the
MARGIN (Pin 3):
Fast Margining Select. In the default same voltage or to a
lower
voltage supply. mode when this pin is floating, the reference voltage
PGOOD (Pin 29):
Power Good. This open-drain output margin offset is changed with MFR_VOUT_COMMAND is pulled down to SGND on start-up and while the out- through the serial interface. If this pin is pulled high, the put voltage is outside the power good window set by reference voltage margin offset is immediately ramped to the PGLIM pin. If the output voltage increases and stays the value pre-stored in the MFR_VOUT_MARGIN_HIGH inside the power good window for more than the delay register. If this pin is pulled low, the reference voltage mar- programmed at the PGFD pin, the PGOOD pin is released. gin offset is immediately ramped to the value pre-stored If the output voltage leaves the power good window for in MFR_VOUT_MARGIN_LOW register. more than 16 switching cycles the PGOOD pin is pulled
WP (Pin 4):
Write Protect Pin. Pulling this pin high dis- down. ables writes to MFR_VOUT_COMMAND, MFR_VOUT_
V
MARGIN_HIGH, and MFR_VOUT_MARGIN_LOW. When
IN (Pin 24):
Signal Input Supply. Decouple this pin to SGND with a capacitor. This pin powers the internal con- this pin is grounded, there are no write restrictions. trol circuitry. This pin is independent of PVIN and may
ALERT (Pin 5):
Open Drain Digital Output. Connect the be connected to the same voltage or to a
higher
supply system SMBALERT interrupt signal to this pin. A pull-up voltage. resistor is required in the application.
PGFD (Pin 25):
PGOOD Deglitch Filter Delay Select. The
CLKOUT (Pin 6):
Clock Out Signal for 2-Phase Operation. voltage at this pin sets the delay that the output must be The phase of this clock is 180° with respect to the internal in regulation before the PGOOD flag is asserted. The delay clock. Signal swing is from VIN to GND. can be programmed to one of seven discrete values where
SDA (Pin 7):
Serial Bus Data Input and Output. A pull-up tDELAY = 200μs • 2N (N = 0 to 5, 7). resistor is required in the application.
RUN_MSTR (Pin 26):
Master Run. The power up thresh-
SCL (Pin 8):
Serial Bus Clock Input. A pull-up resistor is old is set at 1V. When forced below 0.4V, all circuitry is required in the application. shut off and the IC is put into a low current shutdown mode (IQ < 1μA).
MODE/SYNC (Pin 9):
Mode Selection and External Clock Input. If this pin is tied to V
RUN_STBY (Pin 27):
Standby Mode Off. The regulator IN, discontinuous mode is enabled at light loads. If this pin is connected to ground, power up threshold is set at 1V. When forced below 0.4V, forced continuous mode is selected. Driving the MODE/ only the voltage regulator is shut off while the ADC and SYNC pin with an external clock signal will synchronize PMBus interface are still active. When shut off, the ADC the switching frequency to the applied frequency. There refresh rate is reduced to 1Hz and the IC quiescent current is an internal 20k resistor to ground on this pin. Rev B 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information PMBus Command Details Typical Applications Package Description Revision History Typical Application Related Parts
