Datasheet LTC3607 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Dual 600mA 15V Monolithic Synchronous Step-Down DC/DC Regulator |
| Pages / Page | 20 / 6 — pin FuncTions (QFN/MSE). PVIN1, PVIN2, SVIN (Pins 6, 7, 3/Pins 4, 5, 1):. … |
| File Format / Size | PDF / 374 Kb |
| Document Language | English |
pin FuncTions (QFN/MSE). PVIN1, PVIN2, SVIN (Pins 6, 7, 3/Pins 4, 5, 1):. PGOOD1 (Pin 2/Pin 16):. FB2 (Pin 14/Pin 12):
Model Line for this Datasheet
Text Version of Document
LTC3607
pin FuncTions (QFN/MSE) PVIN1, PVIN2, SVIN (Pins 6, 7, 3/Pins 4, 5, 1):
Main Power
PGOOD1 (Pin 2/Pin 16):
Regulator 1 Power Good. This Supply. Must be closely decoupled to GND. These inputs common-drain logic output is pul ed to SGND when the may each be powered from different supply voltages. channel 1 output voltage is not within ±8.5% of regulation. Connect SVIN to either PVIN1 or PVIN2, whichever one
V
is higher. For applications where it’s not known which
FB2 (Pin 14/Pin 12):
Regulator 2 Output Feedback. Receives the feedback voltage from the external resistor PVIN(1 or 2) is higher, connect external diodes between SVIN divider across the regulator 2 output. Nominal voltage for to both PVIN1 and PVIN2 to ensure that SVIN is less than a this pin is 0.6V. diode drop from the higher of PVIN1 or PVIN2.
SW2 (Pin 8/Pin 6):
Regulator 2 Switch Node Connection
PGND1, PGND2, SGND, PGND (Pins 4, 9, 10, 12, Exposed
to the Inductor. This pin switches from PV
Pad Pin 17/Pins 2, 7, 8, 10, Exposed Pad Pin 17):
Main IN2 to PGND2. Ground. Connect to the (–) terminals of COUT1, COUT2, and
RUN2 (Pin 13/Pin 11):
Regulator 2 Enable. Forcing this CIN. The exposed pad must be soldered to PCB ground for pin high (above 3.0V) enables regulator 2, while forcing electrical contact and rated thermal performance. All SGND it to SGND causes regulator 2 to shut down. It is possible and PGND pins must be external y connected to ground. to use a 3.3V source to drive this pin, or tie it to SVIN. An internal soft-start limits the rise time to a minimum
VFB1 (Pin 15/Pin 13):
Regulator 1 Output Feedback. of 0.35ms. Receives the feedback voltage from the external resistor divider across the regulator 1 output. Nominal voltage for
PGOOD2 (Pin 11/Pin 9):
Regulator 2 Power Good. This this pin is 0.6V. common-drain logic output is pul ed to SGND when the channel 2 output voltage is not within ±8.5% of regulation.
SW1 (Pin 5/Pin 3):
Regulator 1 Switch Node Connection to the Inductor. This pin switches from PVIN1 to PGND1.
MODE/SYNC (Pin 1/Pin 15):
Combination Mode Selec- tion and Oscil ator Synchronization. This pin controls the
RUN1 (Pin 16/Pin 14):
Regulator 1 Enable. Forcing this light-load behavior of the device. Forcing this pin to SGND pin high (above 3V) enables regulator 1, while forcing it selects pulse-skipping mode. Floating this pin or forcing to SGND causes regulator 1 to shut down. It is possible it above 1V selects Burst Mode operation. The internal to use a 3.3V source to drive this pin, or tie it to SVIN. oscil ation frequency can be synchronized to an external An internal soft-start limits the rise time to a minimum oscil ator applied to this pin and pulse-skipping mode is of 0.35ms. automatical y selected. 3607fb 6 For more information www.linear.com/LTC3607 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions (QFN/MSE) PVIN1, PVIN2, SVIN (Pins 6, 7, 3/Pins 4, 5, 1):
Main Power
PGOOD1 (Pin 2/Pin 16):
Regulator 1 Power Good. This Supply. Must be closely decoupled to GND. These inputs common-drain logic output is pul ed to SGND when the may each be powered from different supply voltages. channel 1 output voltage is not within ±8.5% of regulation. Connect SVIN to either PVIN1 or PVIN2, whichever one
V
is higher. For applications where it’s not known which
FB2 (Pin 14/Pin 12):
Regulator 2 Output Feedback. Receives the feedback voltage from the external resistor PVIN(1 or 2) is higher, connect external diodes between SVIN divider across the regulator 2 output. Nominal voltage for to both PVIN1 and PVIN2 to ensure that SVIN is less than a this pin is 0.6V. diode drop from the higher of PVIN1 or PVIN2.
SW2 (Pin 8/Pin 6):
Regulator 2 Switch Node Connection
PGND1, PGND2, SGND, PGND (Pins 4, 9, 10, 12, Exposed
to the Inductor. This pin switches from PV
Pad Pin 17/Pins 2, 7, 8, 10, Exposed Pad Pin 17):
Main IN2 to PGND2. Ground. Connect to the (–) terminals of COUT1, COUT2, and
RUN2 (Pin 13/Pin 11):
Regulator 2 Enable. Forcing this CIN. The exposed pad must be soldered to PCB ground for pin high (above 3.0V) enables regulator 2, while forcing electrical contact and rated thermal performance. All SGND it to SGND causes regulator 2 to shut down. It is possible and PGND pins must be external y connected to ground. to use a 3.3V source to drive this pin, or tie it to SVIN. An internal soft-start limits the rise time to a minimum
VFB1 (Pin 15/Pin 13):
Regulator 1 Output Feedback. of 0.35ms. Receives the feedback voltage from the external resistor divider across the regulator 1 output. Nominal voltage for
PGOOD2 (Pin 11/Pin 9):
Regulator 2 Power Good. This this pin is 0.6V. common-drain logic output is pul ed to SGND when the channel 2 output voltage is not within ±8.5% of regulation.
SW1 (Pin 5/Pin 3):
Regulator 1 Switch Node Connection to the Inductor. This pin switches from PVIN1 to PGND1.
MODE/SYNC (Pin 1/Pin 15):
Combination Mode Selec- tion and Oscil ator Synchronization. This pin controls the
RUN1 (Pin 16/Pin 14):
Regulator 1 Enable. Forcing this light-load behavior of the device. Forcing this pin to SGND pin high (above 3V) enables regulator 1, while forcing it selects pulse-skipping mode. Floating this pin or forcing to SGND causes regulator 1 to shut down. It is possible it above 1V selects Burst Mode operation. The internal to use a 3.3V source to drive this pin, or tie it to SVIN. oscil ation frequency can be synchronized to an external An internal soft-start limits the rise time to a minimum oscil ator applied to this pin and pulse-skipping mode is of 0.35ms. automatical y selected. 3607fb 6 For more information www.linear.com/LTC3607 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
