Datasheet LT3692A (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Monolithic Dual Tracking 3.5A Step-Down Switching Regulator |
| Pages / Page | 42 / 9 — pin FuncTions. BST1/BST2:. ILIM1/ILIM2:. CMPI1/CMPI2:. IND1/IND2:. … |
| File Format / Size | PDF / 742 Kb |
| Document Language | English |
pin FuncTions. BST1/BST2:. ILIM1/ILIM2:. CMPI1/CMPI2:. IND1/IND2:. CMPO1/CMPO2:. RT/SYNC:. DIV:. DNC:. GND:. only ground connec-. tion
Model Line for this Datasheet
Text Version of Document
LT3692A
pin FuncTions BST1/BST2:
The BST pin provides a higher than VIN base
ILIM1/ILIM2:
The voltage present at the ILIM pin deter- drive to the power NPN to ensure a low switch drop. If the mines the peak inductor current for the channel. The ILIM voltage between the BST pin and the VIN pin is less than pin is driven by an internal current source with a typical the voltage required to fully turn on the power NPN, the value of 12µA. A resistor from the ILIM pin to ground sets power switch is turned off to recharge the BST capacitor. the ILIM voltage. The maximum current limit range is 4.8A
CMPI1/CMPI2:
The CMPI pin is an input to a compara- to 2A when the ILIM voltages are 1.5V and 0V respectively. tor with a threshold of 720mV and 60mV of hysteresis.
IND1/IND2:
The IND pin is the input to the internal sense Connecting the CMPI pin to the FB pin will generate a resistor that measures current flowing in the inductor. power good signal when the output is within 90% of its When the current in the resistor exceeds the current dic- regulated value. tated by the VC pin, the SW latch is held in reset, disabling
CMPO1/CMPO2:
The CMPO pin is an open-collector the output switch. Bias current flows out of the IND pin. output that sinks current when the CMPI pin falls below
RT/SYNC:
The voltage present at the RT/SYNC pin deter- its threshold. For a typical input voltage above 2.8V, its mines the constant switching frequency. The RT/SYNC output state remains true, although during shutdown, VIN1 pin is driven by an internal current source with a typical undervoltage lockout or thermal shutdown, its current sink value of 12µA which allows a single resistor from the RT/ capability is reduced. The COMPO pins can be left open SYNC pin to ground to set the RT/SYNC voltage and result- circuit or tied together to form a single power good signal. ing switching frequency. Minimum switching frequency
DIV:
The voltage present at the DIV pin determines the ratio is typically 110kHz when VRT/SYNC is 0V and maximum of channel 1 frequency to the master clock frequency set switching frequency is typically 2.5MHz when VRT/SYNC by the RT/SYNC pin. The DIV pin is driven by an internal is above 950mV. current source with a typical value of 12µA which allows Driving the RT/SYNC pin with an external clock signal will a single resistor from the DIV pin to ground to set the synchronize the switch to the applied frequency. Synchro- DIV voltage and resulting channel 1 frequency divider. nization occurs on the rising edge of the clock signal after Ratios of 1, 2, 4 and 8 are available. See the Applications the clock signal is detected. Each rising clock edge initiates Information section for more information. an oscillator ramp reset. A gain control loop servos the
DNC:
Do Not Connect. oscillator charging current to maintain constant oscillator amplitude. Hence, the slope compensation and channel
GND:
The exposed pad pin is the
only ground connec-
phase relationship remain unchanged. If the clock signal
tion
for the device. The exposed pad should be soldered is removed, the oscillator reverts to resistor mode after to a large copper area to reduce thermal resistance. The the synchronization detection circuitry times out. The clock GND pin is common to both channels and also serves as source impedance should be set such that the current out small-signal ground. For ideal operation all small-signal of the RT/SYNC pin in resistor mode generates a frequency ground paths should connect to the GND pin at a single roughly equivalent to the synchronization frequency. See point avoiding any high current ground returns. the Applications Information section for more information.
FB1/FB2:
The FB pin is the negative input to the error am- plifier. The output switches to regulate this pin to 806mV with respect to the exposed ground pad. Bias current flows out of the FB pin. 3692afc For more information www.linear.com/3692A 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions BST1/BST2:
The BST pin provides a higher than VIN base
ILIM1/ILIM2:
The voltage present at the ILIM pin deter- drive to the power NPN to ensure a low switch drop. If the mines the peak inductor current for the channel. The ILIM voltage between the BST pin and the VIN pin is less than pin is driven by an internal current source with a typical the voltage required to fully turn on the power NPN, the value of 12µA. A resistor from the ILIM pin to ground sets power switch is turned off to recharge the BST capacitor. the ILIM voltage. The maximum current limit range is 4.8A
CMPI1/CMPI2:
The CMPI pin is an input to a compara- to 2A when the ILIM voltages are 1.5V and 0V respectively. tor with a threshold of 720mV and 60mV of hysteresis.
IND1/IND2:
The IND pin is the input to the internal sense Connecting the CMPI pin to the FB pin will generate a resistor that measures current flowing in the inductor. power good signal when the output is within 90% of its When the current in the resistor exceeds the current dic- regulated value. tated by the VC pin, the SW latch is held in reset, disabling
CMPO1/CMPO2:
The CMPO pin is an open-collector the output switch. Bias current flows out of the IND pin. output that sinks current when the CMPI pin falls below
RT/SYNC:
The voltage present at the RT/SYNC pin deter- its threshold. For a typical input voltage above 2.8V, its mines the constant switching frequency. The RT/SYNC output state remains true, although during shutdown, VIN1 pin is driven by an internal current source with a typical undervoltage lockout or thermal shutdown, its current sink value of 12µA which allows a single resistor from the RT/ capability is reduced. The COMPO pins can be left open SYNC pin to ground to set the RT/SYNC voltage and result- circuit or tied together to form a single power good signal. ing switching frequency. Minimum switching frequency
DIV:
The voltage present at the DIV pin determines the ratio is typically 110kHz when VRT/SYNC is 0V and maximum of channel 1 frequency to the master clock frequency set switching frequency is typically 2.5MHz when VRT/SYNC by the RT/SYNC pin. The DIV pin is driven by an internal is above 950mV. current source with a typical value of 12µA which allows Driving the RT/SYNC pin with an external clock signal will a single resistor from the DIV pin to ground to set the synchronize the switch to the applied frequency. Synchro- DIV voltage and resulting channel 1 frequency divider. nization occurs on the rising edge of the clock signal after Ratios of 1, 2, 4 and 8 are available. See the Applications the clock signal is detected. Each rising clock edge initiates Information section for more information. an oscillator ramp reset. A gain control loop servos the
DNC:
Do Not Connect. oscillator charging current to maintain constant oscillator amplitude. Hence, the slope compensation and channel
GND:
The exposed pad pin is the
only ground connec-
phase relationship remain unchanged. If the clock signal
tion
for the device. The exposed pad should be soldered is removed, the oscillator reverts to resistor mode after to a large copper area to reduce thermal resistance. The the synchronization detection circuitry times out. The clock GND pin is common to both channels and also serves as source impedance should be set such that the current out small-signal ground. For ideal operation all small-signal of the RT/SYNC pin in resistor mode generates a frequency ground paths should connect to the GND pin at a single roughly equivalent to the synchronization frequency. See point avoiding any high current ground returns. the Applications Information section for more information.
FB1/FB2:
The FB pin is the negative input to the error am- plifier. The output switches to regulate this pin to 806mV with respect to the exposed ground pad. Bias current flows out of the FB pin. 3692afc For more information www.linear.com/3692A 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
