Datasheet LT3507A (Analog Devices) - 9

LT3507A
operation
The LT3507A contains three independent, constant fre- This slave oscillator is normally synchronized to the master quency, current mode, switching regulators with internal oscillator. A comparator senses when VFB is less than 50% power switches plus a low dropout linear regulator. The of its regulated value and switches the regulator from the three regulators share common circuitry including input master oscillator to a slower slave oscillator. VFB is less than source, voltage reference and oscillator, but are otherwise 50% of its regulated value during start-up, short-circuit independent. Operation can be best understood by refer- and overload conditions. Frequency foldback helps limit ring to the Block Diagram (Figure 1). switch current under these conditions. If the RUN pins are tied to ground, the LT3507A is shut The TRK/SS pins override the 0.8V reference for the FB down and draws <1µA from the input source tied to VIN1. If pins when the TRK/SS pins are below 0.8V. This allows any of the RUN pins are driven above 1V, the internal bias either coincident or ratiometric supply tracking on start-up circuits turn on, including the internal regulator, reference, as well as a soft-start capability. and master oscillator. Each switching regulator will only The switch drivers operate either from V begin to operate when its corresponding RUN pin reaches IN or from the BOOST pin. An external capacitor and diode are used to >1.25V. The master oscillator generates three clock signals, generate a voltage at the BOOST pin that is higher than with the signal for channel 1 out of phase by 180°. the input supply. This allows the driver to saturate the The three switchers are current mode regulators. Instead internal bipolar NPN power switch for efficient operation. of directly modulating the duty cycle of the power switch, The BIAS pin allows the internal circuitry to draw its current the feedback loop controls the peak current in the switch from a lower voltage supply than the input, also reducing during each cycle. Compared to voltage mode control, cur- power dissipation and increasing efficiency. If the voltage rent mode control improves loop dynamics and provides on the BIAS pin falls below 3V, then its quiescent current cycle-by-cycle current limit. will flow from VIN. The Block Diagram shows only one of the three step-down A power good comparator trips when the FB pin is at 90% of switching regulators. A pulse from the slave oscillator its regulated value. The PGOOD output is an open-collector sets the RS flip-flop and turns on the internal NPN bipo- transistor that is off when the output is in regulation, al- lar power switch. Current in the switch and the external lowing an external resistor to pull the PGOOD pin high. inductor begins to increase. When this current exceeds a Power good is valid when the LT3507A is enabled and V level determined by the voltage at V IN C, current comparator is within normal operating range. C1 resets the flip-flop, turning off the switch. The current in the inductor flows through the external Schottky diode The LDO regulator uses an external NPN pass transistor to and begins to decrease. The cycle begins again at the next form a linear regulator. The loop is internally compensated pulse from the oscillator. In this way, the voltage on the VC to be stable with a load capacitance of 2.2µF or greater. pin controls the current through the inductor to the output. The LDO is disabled when all three of the RUN pins are low. The internal error amplifier regulates the output voltage by continually adjusting the V The overvoltage and undervoltage detection shuts down C pin voltage. The threshold for switching on the V the LT3507A if the OVLO pin >1.2V or the UVLO pin <1.2V. C pin is >0.9V and an active clamp of 1.8V limits the output current. Input overvoltage and undervoltage values are set by re- sistor dividers to V Each switcher contains an extra, independent oscillator to INSW. Hysteresis is provided by 10µA currents activated when either pin trips. The hysteresis perform frequency foldback during overload conditions. voltage at VIN is the top resistor times 10µA. 3507afa For more information www.linear.com/LT3507A 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Package Description Typical Applications Related Parts