Datasheet ADP5043 (Analog Devices) - 8

ADP5043 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D 1 DE DI MO O ND MR W W M G 20 19 18 17 16 NC 1 15 WSTAT VOUT2 2 14 NC ADP5043 VIN2 3 13 GND TOP VIEW EN2 4 12 WDI2 (Not to Scale) nRSTO 5 11 VOUT1 6 7 8 9 10 N N1 VI I SW ND N1 A V G E P NOTES 1. EXPOSED PAD SHOULD BE CONNECTED TO AGND.
002
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. THE PIN SHOULD BE LEFT FLOATING.
09682- Figure 2. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
1, 14 NC No Connect. Do not connect to this pin. The pin should be left floating. 2 VOUT2 LDO Output Voltage and Sensing Input. 3 VIN2 LDO Input Supply (1.7 V to 5.5 V). 4 EN2 Enable LDO. EN2 = high: turn on the LDO; EN2 = low: turn off the LDO. 5 nRSTO Open-Drain Reset Output, Active Low. 6 AVIN Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V). 7 VIN1 Buck Input Supply (2.3 V to 5.5 V). 8 SW Buck Switching Node. 9 PGND Dedicated Power Ground for Buck Regulator. 10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck. 11 VOUT1 Buck Sensing Node. 12 WDI2 Watchdog 2 (Long Timeout) Refresh Input from Processor. This pin can be disabled only by a factory option. 13, 16 GND Connect to the ground plane. 15 WSTAT Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low: Watchdog 2 timeout. Auto cleared after one second. 17 MODE Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: (auto mode) buck regulator operates in power save mode (PSM) at light load and in constant PWM at higher load. 18 WMOD Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by a three-state condition applied on WDI1. WMOD has an internal 200 kΩ pull-down resistor connected to AGND. 19 WDI1 Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled. 20 MR Manual Reset Input, Active Low. EPAD Exposed Pad. The exposed pad should be connected to analog ground (AGND). Rev. B | Page 8 of 30 Document Outline FEATURES GENERAL DESCRIPTION HIGH LEVEL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS SUPERVISORY SPECIFICATIONS BUCK SPECIFICATIONS LDO SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION SUPERVISORY SECTION Reset Output Manual Reset Input Watchdog 1 Input Watchdog 2 Input Watchdog Status Indicator APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Inductor Output Capacitor Input Capacitor LDO CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties SUPERVISORY SECTION Watchdog 1 Input Current Negative-Going VCC Transients Watchdog Software Considerations PCB LAYOUT GUIDELINES POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature EVALUATION BOARD SCHEMATICS AND ARTWORK SUGGESTED LAYOUT BILL OF MATERIALS APPLICATION DIAGRAM FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE