Datasheet ADP2140 (Analog Devices) - 3

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Data Sheet ADP2140 SPECIFICATIONS
VIN1 = 3.6 V, VIN2 = VOUT2 + 0.3 V or 1.65 V, whichever is greater; 5 V EN1 = EN2 = VIN1; IOUT = 200 mA, IOUT2 = 10 mA, CIN = 10 μF, COUT = 10 µF, COUT2 = 1 µF, LOUT = 1 μH; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
BUCK SECTION Input Voltage Range V 2.3 5.5 V IN1 Buck Output Accuracy V I = 10 mA −1.5 +1.5 % OUT OUT V = 2.3 V or (V + 0.5 V) to 5.5 V, I = 1 mA to 600 mA −2.5 +2.5 % IN1 OUT OUT Transient Load Regulation V V = 1.8 V TR-LOAD OUT Load = 50 mA to 250 mA, rise/fall time = 200 ns 75 mV Load = 200 mA to 600 mA, rise/fall time = 200 ns 75 mV Transient Line Regulation V Line transient = 4 V to 5 V, 4 μs rise time TR-LINE V = 1.0 V 40 mV OUT V = 1.8 V 25 mV OUT V = 3.3 V 25 mV OUT PWM To PSM Threshold V = 2.3 V or (V + 0.5 V) to 5.5 V 100 mA IN1 OUT Output Current I 600 mA OUT Current Limit I V = 2.3 V or (V + 0.5 V) to 5.5 V 1100 1300 mA LIM IN1 OUT Switch On Resistance PFET R V = 2.3 V to 5.5 V 250 mΩ PFET IN1 NFET R V = 2.3 V to 5.5 V 250 mΩ NFET IN1 Switch Leakage Current I EN1 = GND, VIN1 = 5.5 V, and SW = 0 V −1 μA LEAK-SW Quiescent Current I No load, device not switching 20 30 μA Q Minimum On Time ON-TIME 70 ns MIN Oscillator Frequency FREQ 2.55 3.0 3.15 MHz Frequency Foldback Threshold V Output voltage where f ≤ 50% of nominal frequency 50 % FOLD SW Start-Up Time1 t V = 1.8 V, 600 mA load 70 µs START-UP OUT Soft Start Time2 SS V = 1.8 V, 600 mA load 150 μs TIME OUT LDO SECTION Input Voltage Range V 1.65 5.5 V IN2 LDO Output Accuracy V I = 10 mA, T = 25°C −1 +1 % OUT2 OUT2 J 1 mA < I < 300 mA, V = (V + 0.3 V) to 5.5 V, T −1.5 +1.5 % OUT2 IN2 OUT2 J = 25°C 1 mA < I < 300 mA, V = (V + 0.3 V) to 5.5 V −3 +3 % OUT2 IN2 OUT2 Line Regulation ∆V /∆V V = (V + 0.3 V) to 5.5 V, I = 10 mA −0.05 +0.05 %/V OUT2 IN2 IN2 OUT2 OUT2 Load Regulation3 ∆V /∆I I = 1 mA to 300 mA 0.001 0.005 %/mA OUT2 OUT2 OUT2 Dropout Voltage4 V I = 10 mA, V = 1.8 V 4 7 mV DROPOUT OUT2 OUT2 I = 300 mA, V = 1.8 V 110 200 mV OUT2 OUT2 Ground Current I No load, buck disabled 22 35 μA AGND I = 10 mA 65 90 μA OUT2 I = 300 mA 150 220 μA OUT2 Power Supply Rejection Ratio PSRR V = V + 1 V, V = 5 V, I = 10 mA IN2 OUT2 IN1 OUT2 PSRR on V 10 kHz, V = 1.2 V, 1.8 V, 3.3 V 65 dB IN2 OUT2 100 kHz, V = 3.3 V 53 dB OUT2 100 kHz, V = 1.8 V 54 dB OUT2 100 kHz, V = 1.2 V 55 dB OUT2 Rev. A | Page 3 of 32 Document Outline Features Applications General Description Typical Application Circuits Revision History Specifications Recommended Specifications: Capacitors and Inductor Pin Configuration and Function Descriptions Typical Performance Characteristics Buck Output LDO Output Theory of Operation Buck Section Control Scheme PWM Operation PSM Operation Pulse Skipping Threshold Selected Features Short-Circuit Protection Undervoltage Lockout Thermal Protection Soft Start Current Limit Power-Good Pin LDO Section Applications Information Power Sequencing Power-Good Function External Component Selection Selecting the Inductor Output Capacitor Input Capacitor Efficiency Power Switch Conduction Losses Inductor Losses Switching Losses Transition Losses Recommended Buck External Components LDO Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties LDO as a Postregulator to Reduce Buck Output Noise Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide