Datasheet LTC3565 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter |
| Pages / Page | 22 / 7 — PIN FUNCTIONS. RT (Pin 1):. GND (Pin 5, Exposed Pad Pin 11):. RUN (Pin … |
| File Format / Size | PDF / 824 Kb |
| Document Language | English |
PIN FUNCTIONS. RT (Pin 1):. GND (Pin 5, Exposed Pad Pin 11):. RUN (Pin 2):. PVIN (Pin 6):. SVIN (Pin 7):. SYNC/MODE (Pin 3):
Model Line for this Datasheet
Text Version of Document
LTC3565
PIN FUNCTIONS RT (Pin 1):
Timing Resistor Pin. The oscillator frequency
GND (Pin 5, Exposed Pad Pin 11):
Main Power Ground is programmed by connecting a resistor from this pin to Pin. Connect to the (–) terminal of COUT, and (–) terminal ground. of CIN. The exposed pad must be soldered to electrical
RUN (Pin 2):
Converter Enable Pin. Forcing this pin above ground on the PCB. 1.5V enables this part, while forcing it below 0.3V causes
PVIN (Pin 6):
Main Supply Pin. Must be closely decoupled the device to shut down. In shutdown, the device draws to GND. <1µA supply current. This pin must be driven; do not float.
SVIN (Pin 7):
The Signal Power Pin. All active circuitry is
SYNC/MODE (Pin 3):
Combination Mode Selection and powered from this pin. Must be closely decoupled to GND. Oscillator Synchronization Pin. This pin controls the SVIN must be greater than or equal to PVIN. operation of the device. When tied to SVIN or GND, Burst
PGOOD (Pin 8):
The Power Good Pin. This common drain Mode operation or pulse skipping mode is selected, logic output is pulled to GND when the output voltage is respectively. If this pin is held at half of SVIN, the forced not within ±7% of regulation. continuous mode is selected. The oscillation frequency can be synchronized to an external oscillator applied to
VFB (Pin 9):
Receives the feedback voltage from the ex- this pin. When synchronized to an external clock, pulse ternal resistive divider across the output. Nominal voltage skip mode is selected. for this pin is 0.6V.
SW (Pin 4):
The Switch Node Connection to the Inductor.
ITH (Pin 10):
Error Amplifier Compensation Point. The This pin swings from PVIN to GND. current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0.4V to 1.4V.
NOMINAL (V) ABSOLUTE MAX (V) PIN NAME DESCRIPTION MIN TYP MAX MIN MAX
1 RT Timing Resistor –0.3 0.4 SVIN –0.3 SVIN + 0.3 2 RUN Enable Pin –0.3 SVIN –0.3 SVIN 3 SYNC/MODE Mode Select/Synchronization Pin 0 SVIN –0.3 SVIN + 0.3 4 SW Switch Node 0 PVIN –0.3 PVIN + 0.3 5 GND Main Power Ground 0 6 PVIN Main Power Supply –0.3 5.5 –0.3 6 7 SVIN Signal Power Supply 2.5 5.5 –0.3 6 8 PGOOD Power Good Pin 0 SVIN –0.3 SVIN + 0.3 9 VFB Output Feedback Pin 0 0.8 1.0 –0.3 SVIN + 0.3 10 ITH Error Amplifier Compensation 0 1.5 –0.3 SVIN + 0.3 3565fc For more information www.linear.com/LTC3565 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Application Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS RT (Pin 1):
Timing Resistor Pin. The oscillator frequency
GND (Pin 5, Exposed Pad Pin 11):
Main Power Ground is programmed by connecting a resistor from this pin to Pin. Connect to the (–) terminal of COUT, and (–) terminal ground. of CIN. The exposed pad must be soldered to electrical
RUN (Pin 2):
Converter Enable Pin. Forcing this pin above ground on the PCB. 1.5V enables this part, while forcing it below 0.3V causes
PVIN (Pin 6):
Main Supply Pin. Must be closely decoupled the device to shut down. In shutdown, the device draws to GND. <1µA supply current. This pin must be driven; do not float.
SVIN (Pin 7):
The Signal Power Pin. All active circuitry is
SYNC/MODE (Pin 3):
Combination Mode Selection and powered from this pin. Must be closely decoupled to GND. Oscillator Synchronization Pin. This pin controls the SVIN must be greater than or equal to PVIN. operation of the device. When tied to SVIN or GND, Burst
PGOOD (Pin 8):
The Power Good Pin. This common drain Mode operation or pulse skipping mode is selected, logic output is pulled to GND when the output voltage is respectively. If this pin is held at half of SVIN, the forced not within ±7% of regulation. continuous mode is selected. The oscillation frequency can be synchronized to an external oscillator applied to
VFB (Pin 9):
Receives the feedback voltage from the ex- this pin. When synchronized to an external clock, pulse ternal resistive divider across the output. Nominal voltage skip mode is selected. for this pin is 0.6V.
SW (Pin 4):
The Switch Node Connection to the Inductor.
ITH (Pin 10):
Error Amplifier Compensation Point. The This pin swings from PVIN to GND. current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0.4V to 1.4V.
NOMINAL (V) ABSOLUTE MAX (V) PIN NAME DESCRIPTION MIN TYP MAX MIN MAX
1 RT Timing Resistor –0.3 0.4 SVIN –0.3 SVIN + 0.3 2 RUN Enable Pin –0.3 SVIN –0.3 SVIN 3 SYNC/MODE Mode Select/Synchronization Pin 0 SVIN –0.3 SVIN + 0.3 4 SW Switch Node 0 PVIN –0.3 PVIN + 0.3 5 GND Main Power Ground 0 6 PVIN Main Power Supply –0.3 5.5 –0.3 6 7 SVIN Signal Power Supply 2.5 5.5 –0.3 6 8 PGOOD Power Good Pin 0 SVIN –0.3 SVIN + 0.3 9 VFB Output Feedback Pin 0 0.8 1.0 –0.3 SVIN + 0.3 10 ITH Error Amplifier Compensation 0 1.5 –0.3 SVIN + 0.3 3565fc For more information www.linear.com/LTC3565 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Application Package Description Revision History Typical Application Related Parts
