Datasheet LTC3407A-2 (Analog Devices) - 10

LTC3407A-2
U U W U APPLICATIO S I FOR ATIO
At worst, the ringing at the input can be large enough to
Power-On Reset
damage the part. The POR pin is an open-drain output which pulls low when Since the ESR of a ceramic capacitor is so low, the input either regulator is out of regulation. When both output and output capacitor must instead fulfill a charge storage voltages are within ±8.5% of regulation, a timer is started requirement. During a load step, the output capacitor must which releases POR after 216 clock cycles (about 29ms in instantaneously supply the current to support the load pulse skipping mode). This delay can be significantly until the feedback loop raises the switch current enough to longer in Burst Mode operation with low load currents, support the load. The time required for the feedback loop since the clock cycles only occur during a burst and there to respond is dependent on the compensation and the could be milliseconds of time between bursts. This can be output capacitor size. Typically, 3-4 cycles are required to bypassed by tying the POR output to the MODE/SYNC respond to a load step, but only in the first cycle does the input, to force pulse skipping mode during a reset. In output drop linearly. The output droop, VDROOP, is usually addition, if the output voltage faults during Burst Mode about 3 times the linear drop of the first cycle. Thus, a good sleep, POR could have a slight delay for an undervoltage place to start is with the output capacitor size of approxi- output condition and may not respond to an overvoltage mately: output. This can be avoided by using pulse skipping mode I Δ instead. When either channel is shut down, the POR C OUT ≈ OUT 3 output is pulled low, since one or both of the channels are f • V O DROOP not in regulation. More capacitance may be required depending on the duty cycle and load step requirements.
Mode Selection & Frequency Synchronization
In most applications, the input capacitor is merely re- The MODE/SYNC pin is a multipurpose pin which provides quired to supply high frequency bypassing, since the mode selection and frequency synchronization. Connect- impedance to the supply is very low. A 10μF ceramic ing this pin to VIN enables Burst Mode operation, which capacitor is usually enough for these conditions. provides the best low current efficiency at the cost of a higher output voltage ripple. When this pin is connected to
Setting the Output Voltage
ground, pulse skipping operation is selected which pro- The LTC3407A-2 develops a 0.6V reference voltage be- vides the lowest output ripple, at the cost of low current tween the feedback pin, V efficiency. FB, and ground as shown in Figure 1. The output voltage is set by a resistive divider The LTC3407A-2 can also be synchronized to another according to the following formula: LTC3407A-2 by the MODE/SYNC pin. During synchroni- zation, the mode is set to pulse skipping and the top switch ⎛ R2⎞ V = 0 6 . V 1+ OUT turn-on is synchronized to the rising edge of the external ⎝⎜ R1⎠⎟ clock. Keeping the current small (<5μA) in these resistors maxi-
Checking Transient Response
mizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the The regulator loop response can be checked by looking at phase margin of the error amp loop. the load transient response. Switching regulators take To improve the frequency response, a feed-forward ca- several cycles to respond to a step in load current. When pacitor C a load step occurs, V F may also be used. Great care should be taken to OUT immediately shifts by an amount route the V equal to FB line away from noise sources, such as the ΔILOAD • ESR, where ESR is the effective series inductor or the SW line. resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During 3407a2f 10